Registers 'r0' till 'r3' are scratch registers and do not need to be
restored.
Signed-off-by: Enrico Scholz <enrico.sch...@sigma-chemnitz.de>
---
arch/arm/cpu/cache-armv7.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/cache-armv7.S b/arch/arm/cpu/cache-armv7.S
index 5bdf7e4..5595cf6 100644
--- a/arch/arm/cpu/cache-armv7.S
+++ b/arch/arm/cpu/cache-armv7.S
@@ -65,7 +65,7 @@ ENTRY(v7_mmu_cache_flush)
mcr p15, 0, r12, c7, c14, 0 @ clean+invalidate D
b iflush
hierarchical:
- stmfd sp!, {r0-r7, r9-r11}
+ stmfd sp!, {r4-r7, r9-r11}
mcr p15, 0, r12, c7, c10, 5 @ DMB
mrc p15, 1, r0, c0, c0, 1 @ read clidr
ands r3, r0, #0x7000000 @ extract loc from clidr
@@ -107,7 +107,7 @@ skip:
cmp r3, r12
bgt loop1
finished:
- ldmfd sp!, {r0-r7, r9-r11}
+ ldmfd sp!, {r4-r7, r9-r11}
mov r12, #0 @ switch back to cache level 0
mcr p15, 2, r12, c0, c0, 0 @ select current cache level in
cssr
iflush:
--
1.8.1.4
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