In omap4_enable_all_clocks we not only enable the mcbsp clocks, but also
change the source from ABE_24M_FCLK to 24M_FCLK. Revert this and default
to the reset state.
Signed-off-by: Jan Weitzel <j.weit...@phytec.de>
---
arch/arm/mach-omap/omap4_clock.c | 6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap/omap4_clock.c b/arch/arm/mach-omap/omap4_clock.c
index 0621fd3..889d1f9 100644
--- a/arch/arm/mach-omap/omap4_clock.c
+++ b/arch/arm/mach-omap/omap4_clock.c
@@ -253,9 +253,9 @@ void omap4_enable_all_clocks(void)
sr32(CM1_ABE_PDM_CLKCTRL, 0, 32, 0x2);
sr32(CM1_ABE_DMIC_CLKCTRL, 0, 32, 0x2);
sr32(CM1_ABE_MCASP_CLKCTRL, 0, 32, 0x2);
- sr32(CM1_ABE_MCBSP1_CLKCTRL, 0, 32, 0x08000002);
- sr32(CM1_ABE_MCBSP2_CLKCTRL, 0, 32, 0x08000002);
- sr32(CM1_ABE_MCBSP3_CLKCTRL, 0, 32, 0x08000002);
+ sr32(CM1_ABE_MCBSP1_CLKCTRL, 0, 32, 0x2);
+ sr32(CM1_ABE_MCBSP2_CLKCTRL, 0, 32, 0x2);
+ sr32(CM1_ABE_MCBSP3_CLKCTRL, 0, 32, 0x2);
sr32(CM1_ABE_SLIMBUS_CLKCTRL, 0, 32, 0xf02);
sr32(CM1_ABE_TIMER5_CLKCTRL, 0, 32, 0x2);
sr32(CM1_ABE_TIMER6_CLKCTRL, 0, 32, 0x2);
--
1.7.0.4
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