Because the port count is different between the MPC8544 and
existing CPU support, the Ethernet port count is defined on
a per CPU basis.
Accordingly, the TBI PHY initialisation code is updated.
Signed-off-by: Renaud Barbier <renaud.barb...@ge.com>
---
arch/ppc/mach-mpc85xx/eth-devices.c | 2 +-
.../ppc/mach-mpc85xx/include/mach/config_mpc85xx.h | 2 ++
2 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/arch/ppc/mach-mpc85xx/eth-devices.c
b/arch/ppc/mach-mpc85xx/eth-devices.c
index 611a578..efebe11 100644
--- a/arch/ppc/mach-mpc85xx/eth-devices.c
+++ b/arch/ppc/mach-mpc85xx/eth-devices.c
@@ -40,7 +40,7 @@ static int fsl_phy_init(void)
add_generic_device("gfar-mdio", 0, NULL, MDIO_BASE_ADDR,
0x1000, IORESOURCE_MEM, NULL);
- for (i = 1; i < 3; i++) {
+ for (i = 1; i < FSL_NUM_TSEC; i++) {
out_be32(base + (i * 0x1000), GFAR_TBIPA_END - i);
/* Use "gfar-tbiphy" devices to access internal PHY. */
add_generic_device("gfar-tbiphy", i, NULL,
diff --git a/arch/ppc/mach-mpc85xx/include/mach/config_mpc85xx.h
b/arch/ppc/mach-mpc85xx/include/mach/config_mpc85xx.h
index 7cdb37f..7d606d1 100644
--- a/arch/ppc/mach-mpc85xx/include/mach/config_mpc85xx.h
+++ b/arch/ppc/mach-mpc85xx/include/mach/config_mpc85xx.h
@@ -28,10 +28,12 @@
#define MAX_CPUS 2
#define FSL_NUM_LAWS 12
#define FSL_SEC_COMPAT 2
+#define FSL_NUM_TSEC 3
#elif defined(CONFIG_MPC8544)
#define MAX_CPUS 1
#define FSL_NUM_LAWS 10
+#define FSL_NUM_TSEC 2
#else
#error Processor type not defined for this platform
--
1.7.1
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