+ Teresa, Jan and Christian
On Fri, Jan 23, 2015 at 02:48:55PM +0300, Dmitry Lavnikevich wrote:
> NAND chip used on phyFLEX-i.MX6 with 4GB NAND (MT29F32G08AFACAWP) has
> 512k eraseblock size.
>
> Align NAND partitions by 512k to fix erase fails.
>
> Signed-off-by: Dmitry Lavnikevich <d.lavnikev...@sam-solutions.com>
> ---
> arch/arm/dts/imx6qdl-phytec-pfla02.dtsi | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
> b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
> index 32ce088fee48..52b279057a33 100644
> --- a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
> +++ b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
> @@ -95,22 +95,22 @@
>
> partition@1 {
> label = "barebox-environment";
> - reg = <0x400000 0x20000>;
> + reg = <0x400000 0x80000>;
> };
>
> partition@2 {
> label = "oftree";
> - reg = <0x420000 0x20000>;
> + reg = <0x480000 0x80000>;
> };
The partition size for barebox-environment and the devicetree used to be
one eraseblock only. Now it's again only one eraseblock at least for the
4k Page size variants. If one of those blocks is bad the board becomes
unusable. I think the partitions should be at least two eraseblocks.
That of course would make them quite big.
Any opinions about this?
Sascha
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