Hi,
On 09/30/2017 01:57 PM, Antony Pavlov wrote:
On Fri, 29 Sep 2017 14:07:09 +0200
Oleksij Rempel <li...@rempel-privat.de> wrote:
Hi,
hm... mostly looks identical with existing arch
What do you mean when you say "existing arch"?
...
Am 29.09.2017 um 01:12 schrieb Antony Pavlov:
...
diff --git a/arch/riscv/boot/start.S b/arch/riscv/boot/start.S
new file mode 100644
index 000000000..2fd00f63d
--- /dev/null
+++ b/arch/riscv/boot/start.S
@@ -0,0 +1,74 @@
+/*
+ * Startup Code for MIPS CPU
+ *
+ * based on coreboot/src/arch/riscv/bootblock.S
+ *
+ * Copyright (C) 2016 Antony Pavlov <antonynpav...@gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <asm-generic/memory_layout.h>
+
+ .text
+ .section ".text_entry"
+ .align 2
+
+.globl _start
+_start:
+ li sp, STACK_BASE + STACK_SIZE
+
+ # make room for HLS and initialize it
+ addi sp, sp, -64 /* MENTRY_FRAME_SIZE */
+
+ # poison the stack
+ li t1, STACK_BASE
+ li t0, 0xdeadbeef
+ sw t0, 0(t1)
+
+ # clear any pending interrupts
+ //csrwi mip, 0
should be removed.
Actually not!
I have imported this code from coreboot.
I have commented this line because csrwi does not worked in some cases.
But I have to make additional investigations on csrwi.
CSRRWI is part of the base integer instruction set and the machine mode
is mandatory. If there are troubles with this instruction, the core has
a faulty design. So executing this line should be okay even if there is
no interrupt controller.
--
Mit freundlichen Grüßen,
With best regards,
Daniel Schultz
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