Port of a Linux commit b6b18f589e1ddbfbc31f72ea7fb8a723a2d10058
Add sanity checks on "addr" input parameter in dw_pcie_cfg_read() and
dw_pcie_cfg_write(). These checks make sure that accesses are aligned on
their size, e.g., a 4-byte config access is aligned on a 4-byte boundary.
[bhelgaas: changelog, set *val = 0 in failure case]
Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelg...@google.com>
Acked-by: Pratyush Anand <pratyush.an...@gmail.com>
Signed-off-by: Andrey Smirnov <andrew.smir...@gmail.com>
---
drivers/pci/pcie-designware.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/pci/pcie-designware.c b/drivers/pci/pcie-designware.c
index f46d33265..f47e5eb1e 100644
--- a/drivers/pci/pcie-designware.c
+++ b/drivers/pci/pcie-designware.c
@@ -76,6 +76,11 @@ static unsigned long global_io_offset;
int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
{
+ if ((uintptr_t)addr & (size - 1)) {
+ *val = 0;
+ return PCIBIOS_BAD_REGISTER_NUMBER;
+ }
+
if (size == 4)
*val = readl(addr);
else if (size == 2)
@@ -92,6 +97,9 @@ int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val)
{
+ if ((uintptr_t)addr & (size - 1))
+ return PCIBIOS_BAD_REGISTER_NUMBER;
+
if (size == 4)
writel(val, addr);
else if (size == 2)
--
2.19.1
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