From: Rouven Czerwinski <[email protected]> As our assembly routines are now written to work correctly on 32-bit as well as 64-bit, nothing is holding us back from adding 64-bit support.
Signed-off-by: Rouven Czerwinski <[email protected]> Signed-off-by: Ahmad Fatoum <[email protected]> --- arch/riscv/Kconfig | 27 +++++++++++++++++++-------- arch/riscv/Makefile | 7 +++++-- arch/riscv/include/asm/elf.h | 1 - arch/riscv/include/asm/types.h | 8 +------- arch/riscv/lib/barebox.lds.S | 5 +++++ arch/riscv/lib/pbl.lds.S | 5 +++++ 6 files changed, 35 insertions(+), 18 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 91e8546f9624..08a0e7cef48d 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -11,6 +11,7 @@ config RISCV select HAVE_PBL_IMAGE select HAVE_PBL_MULTI_IMAGES select HAVE_IMAGE_COMPRESSION + select HAS_ARCH_SJLJ select HAS_KALLSYMS config ARCH_TEXT_BASE @@ -25,6 +26,7 @@ choice config MACH_ERIZO bool "erizo family" + select ARCH_RV32I select HAS_DEBUG_LL select HAS_NMON select USE_COMPRESSED_DTB @@ -41,24 +43,33 @@ config ARCH_RV32I select GENERIC_LIB_ASHLDI3 select GENERIC_LIB_ASHRDI3 select GENERIC_LIB_LSHRDI3 - select HAS_ARCH_SJLJ + select 32BIT + +config ARCH_RV64I + bool "RV64I" + select CPU_SUPPORTS_64BIT_KERNEL + select 64BIT endchoice config CPU_SUPPORTS_32BIT_KERNEL bool -choice - prompt "barebox code model" - default 32BIT +config CPU_SUPPORTS_64BIT_KERNEL + bool + +config PHYS_ADDR_T_64BIT + bool config 32BIT - bool "32-bit barebox" + bool depends on CPU_SUPPORTS_32BIT_KERNEL - help - Select this option to build a 32-bit barebox. -endchoice +config 64BIT + bool + depends on CPU_SUPPORTS_64BIT_KERNEL + select ARCH_DMA_ADDR_T_64BIT + select PHYS_ADDR_T_64BIT source "arch/riscv/mach-erizo/Kconfig" diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 00456ed02ce1..c49c1b09ec8e 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -3,8 +3,11 @@ KBUILD_DEFCONFIG := erizo_generic_defconfig KBUILD_CPPFLAGS += -fno-strict-aliasing ifeq ($(CONFIG_ARCH_RV32I),y) - riscv-cflags-y := -march=rv32im -mabi=ilp32 - riscv-ldflags-y := -melf32lriscv + riscv-cflags-y += -march=rv32im -mabi=ilp32 + riscv-ldflags-y += -melf32lriscv +else + riscv-cflags-y += -march=rv64im -mabi=lp64 + riscv-ldflags-y += -melf64lriscv endif riscv-cflags-y += -Wstrict-prototypes -mcmodel=medany -fpic diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h index adb8ec8f6ece..0cd27724da60 100644 --- a/arch/riscv/include/asm/elf.h +++ b/arch/riscv/include/asm/elf.h @@ -4,7 +4,6 @@ #if __SIZEOF_POINTER__ == 8 #define ELF_CLASS ELFCLASS64 -#define CONFIG_PHYS_ADDR_T_64BIT #else #define ELF_CLASS ELFCLASS32 #endif diff --git a/arch/riscv/include/asm/types.h b/arch/riscv/include/asm/types.h index af37d7738c65..1ad5904f9178 100644 --- a/arch/riscv/include/asm/types.h +++ b/arch/riscv/include/asm/types.h @@ -3,18 +3,12 @@ #include <asm-generic/int-ll64.h> -#ifdef __riscv64 +#if __riscv_xlen == 64 /* * This is used in dlmalloc. On RISCV64 we need it to be 64 bit */ #define INTERNAL_SIZE_T unsigned long -/* - * This is a Kconfig variable in the Kernel, but we want to detect - * this during compile time, so we set it here. - */ -#define CONFIG_PHYS_ADDR_T_64BIT - #endif #endif /* __ASM_RISCV_TYPES_H */ diff --git a/arch/riscv/lib/barebox.lds.S b/arch/riscv/lib/barebox.lds.S index 562ad5dc6662..7856b57a5220 100644 --- a/arch/riscv/lib/barebox.lds.S +++ b/arch/riscv/lib/barebox.lds.S @@ -15,6 +15,11 @@ OUTPUT_ARCH(riscv) ENTRY(start) +#ifdef CONFIG_64BIT +OUTPUT_FORMAT("elf64-littleriscv") +#else +OUTPUT_FORMAT("elf32-littleriscv") +#endif SECTIONS { . = 0x0; diff --git a/arch/riscv/lib/pbl.lds.S b/arch/riscv/lib/pbl.lds.S index 881faac34064..e238b2bfd34e 100644 --- a/arch/riscv/lib/pbl.lds.S +++ b/arch/riscv/lib/pbl.lds.S @@ -6,6 +6,11 @@ #include <asm-generic/memory_layout.h> OUTPUT_ARCH(riscv) +#ifdef CONFIG_64BIT +OUTPUT_FORMAT("elf64-littleriscv") +#else +OUTPUT_FORMAT("elf32-littleriscv") +#endif SECTIONS { . = 0x0; -- 2.29.2 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
