To make changes to the SDRAM controller effective, the APPLYCFG bit must
be set after programming the bitstream to the FPGA. This has to be done
without any SDRAM usage. Therefore copy the function to execute to the
OCRAM and execute it from there.
Signed-off-by: Steffen Trumtrar <s.trumt...@pengutronix.de>
---
Notes:
v1: Link:
https://lore.barebox.org/20210618080939.15343-2-s.trumt...@pengutronix.de
Changes since v1:
- include feedback from Ahmad
.../mach-socfpga/include/mach/cyclone5-regs.h | 1 +
drivers/firmware/Makefile | 2 +-
drivers/firmware/socfpga.c | 21 +++++++++++++++++++
drivers/firmware/socfpga_sdr.S | 20 ++++++++++++++++++
4 files changed, 43 insertions(+), 1 deletion(-)
create mode 100644 drivers/firmware/socfpga_sdr.S
diff --git a/arch/arm/mach-socfpga/include/mach/cyclone5-regs.h
b/arch/arm/mach-socfpga/include/mach/cyclone5-regs.h
index e88daf718917..1a7d787a27bf 100644
--- a/arch/arm/mach-socfpga/include/mach/cyclone5-regs.h
+++ b/arch/arm/mach-socfpga/include/mach/cyclone5-regs.h
@@ -18,5 +18,6 @@
#define CYCLONE5_SYSMGR_ADDRESS 0xffd08000
#define CYCLONE5_SCANMGR_ADDRESS 0xfff02000
#define CYCLONE5_SMP_TWD_ADDRESS 0xfffec600
+#define CYCLONE5_OCRAM_ADDRESS 0xffff0000
#endif /* __MACH_SOCFPGA_REGS_H */
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index b162b08b0a80..bbd2bcda9780 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -1,3 +1,3 @@
obj-$(CONFIG_FIRMWARE_ALTERA_SERIAL) += altera_serial.o
-obj-$(CONFIG_FIRMWARE_ALTERA_SOCFPGA) += socfpga.o
+obj-$(CONFIG_FIRMWARE_ALTERA_SOCFPGA) += socfpga.o socfpga_sdr.o
obj-$(CONFIG_FIRMWARE_ZYNQMP_FPGA) += zynqmp-fpga.o
diff --git a/drivers/firmware/socfpga.c b/drivers/firmware/socfpga.c
index 61c2b02eca42..b16bd33de408 100644
--- a/drivers/firmware/socfpga.c
+++ b/drivers/firmware/socfpga.c
@@ -39,6 +39,9 @@
#include <mach/cyclone5-reset-manager.h>
#include <mach/cyclone5-regs.h>
#include <mach/cyclone5-sdram.h>
+#include <asm/fncpy.h>
+#include <mmu.h>
+#include <asm/cache.h>
#define FPGAMGRREGS_STAT 0x0
#define FPGAMGRREGS_CTRL 0x4
@@ -78,6 +81,10 @@
#define CDRATIO_x4 0x2
#define CDRATIO_x8 0x3
+extern void socfpga_sdram_apply_static_cfg(void __iomem *sdrctrlgrp);
+extern void socfpga_sdram_apply_static_cfg_end(void *);
+extern const u32 socfpga_sdram_apply_static_cfg_sz;
+
struct fpgamgr {
struct firmware_handler fh;
struct device_d dev;
@@ -345,6 +352,7 @@ static int socfpga_fpgamgr_program_finish(struct
firmware_handler *fh)
{
struct fpgamgr *mgr = container_of(fh, struct fpgamgr, fh);
int status;
+ void (*ocram_func)(void __iomem *ocram_base);
/* Ensure the FPGA entering config done */
status = socfpga_fpgamgr_program_poll_cd(mgr);
@@ -374,6 +382,19 @@ static int socfpga_fpgamgr_program_finish(struct
firmware_handler *fh)
return status;
}
+ remap_range((void *)CYCLONE5_OCRAM_ADDRESS, PAGE_SIZE, MAP_CACHED);
+
+ dev_dbg(&mgr->dev, "Setting APPLYCFG bit...\n");
+
+ ocram_func = fncpy((void __iomem *)CYCLONE5_OCRAM_ADDRESS,
+ &socfpga_sdram_apply_static_cfg,
+ socfpga_sdram_apply_static_cfg_sz);
+
+ sync_caches_for_execution();
+
+ ocram_func((void __iomem *) (CYCLONE5_SDR_ADDRESS +
+ SDR_CTRLGRP_STATICCFG_ADDRESS));
+
return 0;
}
diff --git a/drivers/firmware/socfpga_sdr.S b/drivers/firmware/socfpga_sdr.S
new file mode 100644
index 000000000000..b895fb293cbd
--- /dev/null
+++ b/drivers/firmware/socfpga_sdr.S
@@ -0,0 +1,20 @@
+#include <linux/linkage.h>
+
+ .arch armv7-a
+ .arm
+
+/*
+ * r0 : sdram controller staticcfg
+ */
+
+ENTRY(socfpga_sdram_apply_static_cfg)
+ push {ip,lr}
+ ldr r1, [r0]
+ orr r1, r1, #8
+ str r1, [r0]
+ pop {ip,pc}
+ .align
+ENDPROC(socfpga_sdram_apply_static_cfg)
+
+ENTRY(socfpga_sdram_apply_static_cfg_sz)
+ .word . - socfpga_sdram_apply_static_cfg;
--
2.30.2
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