Le Fri, 14 Jan 2022 17:54:56 +0100, Jules Maselbas <[email protected]> a écrit :
> + apb {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + gpio0: gpio@20230000 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0x0 0x20230000 0x0 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + gpio0_banka: gpio-controller@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + #address-cells = <0>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + snps,nr-gpios = <32>;
> + snps,has-pinctrl;
> + reg = <0>;
> + interrupt-parent = <&itgen_soc_periph0>;
> + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
> + /* All pins of port A are interrupt
> capable */
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + uart0_pins: pinmux_uart0_pins {
> + function = "hw";
> + pins = "pin0", "pin1";
> + };
> + uart1_pins: pinmux_uart1_pins {
> + function = "hw";
> + pins = "pin2", "pin3";
> + };
> + uart2_pins: pinmux_uart2_pins {
> + function = "hw";
> + pins = "pin4", "pin5";
> + };
> + can0_pins: pinmux_can0_pins {
> + function = "hw";
> + pins = "pin6", "pin7";
> + };
> + can1_pins: pinmux_can1_pins {
> + function = "hw";
> + pins = "pin8", "pin9";
> + };
> + i2c0_pins: pinmux_i2c0_pins {
> + function = "hw";
> + pins = "pin10", "pin11";
> + };
> + smb1_pins: pinmux_smb1_pins {
> + function = "hw";
> + pins = "pin12", "pin13";
> + };
> + smb2_pins: pinmux_smb2_pins {
> + function = "hw";
> + pins = "pin14", "pin15";
> + };
> +
> qspi0_master_pins:pinmux_qspi0_master_pins {
> + function = "hw";
> + pins = "pin18", "pin19",
> "pin20", "pin21", "pin22", "pin23", "pin24";
> + };
> + spi_slave_pins:pinmux_spi_slave_pins {
> + function = "hw";
> + pins = "pin25", "pin26",
> "pin27", "pin28";
> + };
> + timer0_pins:pinmux_timer0_pins {
> + function = "hw";
> + pins = "pin29";
> + };
> + timer1_pins:pinmux_timer1_pins {
> + function = "hw";
> + pins = "pin30";
> + };
> + timer2_pins:pinmux_timer2_pins {
> + function = "hw";
> + pins = "pin31";
> + };
Hi Jules,
I'm afraid this won't work at all since the upstream
snps,dw-apb-gpio compatible driver does not handle pinctrl yet. The
support for that is in your private tree I guess [1].
Clément
[1]
https://github.com/kalray/barebox/blob/coolidge/drivers/pinctrl/pinctrl-dw.c
> + };
> + };
> +
> + gpio1: gpio@20231000 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0x0 0x20231000 0x0 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + gpio1_banka: gpio-controller@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + #address-cells = <0>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + snps,nr-gpios = <32>;
> + snps,has-pinctrl;
> + reg = <0>;
> + interrupt-parent = <&itgen_soc_periph0>;
> + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
> + /* All pins of port A are interrupt
> capable */
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + uart3_pins: pinmux_uart3_pins {
> + function = "hw";
> + pins = "pin0", "pin1";
> + };
> + uart4_pins: pinmux_uart4_pins {
> + function = "hw";
> + pins = "pin2", "pin3";
> + };
> + uart5_pins: pinmux_uart5_pins {
> + function = "hw";
> + pins = "pin4", "pin5";
> + };
> + can2_pins: pinmux_can2_pins {
> + function = "hw";
> + pins = "pin6", "pin7";
> + };
> + can3_pins: pinmux_can3_pins {
> + function = "hw";
> + pins = "pin8", "pin9";
> + };
> + i2c3_pins: pinmux_i2c3_pins {
> + function = "hw";
> + pins = "pin10", "pin11";
> + };
> + smb4_pins: pinmux_smb4_pins {
> + function = "hw";
> + pins = "pin12", "pin13";
> + };
> + timer3_pins:pinmux_timer3_pins {
> + function = "hw";
> + pins = "pin15";
> + };
> + timer4_pins:pinmux_timer4_pins {
> + function = "hw";
> + pins = "pin16";
> + };
> + timer5_pins:pinmux_timer5_pins {
> + function = "hw";
> + pins = "pin17";
> + };
> +
> qspi1_master_pins:pinmux_qspi1_master_pins {
> + function = "hw";
> + pins = "pin18", "pin19",
> "pin20", "pin21", "pin22", "pin23", "pin24";
> + };
> +
> qspi2_master_pins:pinmux_qspi2_master_pins {
> + function = "hw";
> + pins = "pin25", "pin26",
> "pin27", "pin28", "pin29", "pin30", "pin31";
> + };
> + };
> + };
> };
> };
> };
--
Clément Léger,
Embedded Linux and Kernel engineer at Bootlin
https://bootlin.com
_______________________________________________
barebox mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/barebox
