On Thu, Jun 16, 2022 at 04:05:20PM +0200, Marco Felsch wrote: > This commit is based on commit dd977acd6 ("clk: imx8mp: remove SYS PLL > 1/2 clock gates") and adopts kernel commit: > > | commit d25cbd3e392730f459f1fbf5f959c16b460a59ca > | Author: Peng Fan <peng....@nxp.com> > | AuthorDate: Fri Feb 25 16:17:31 2022 +0800 > | Commit: Abel Vesa <abel.v...@nxp.com> > | CommitDate: Fri Mar 4 17:06:29 2022 +0200 > | > | clk: imx8mm: remove SYS PLL 1/2 clock gates > | > | Remove the PLL 1/2 gates as it make AMP clock management harder without > | obvious benifit. > | > | Signed-off-by: Peng Fan <peng....@nxp.com> > | Reviewed-by: Abel Vesa <abel.v...@nxp.com> > | Link: > https://lore.kernel.org/r/20220225081733.2294166-2-peng....@oss.nxp.com > | Signed-off-by: Abel Vesa <abel.v...@nxp.com> > > Unlike the original patch this one also makes sure that the removed > gates are enabled as they are needed for their consumers. > > Signed-off-by: Marco Felsch <m.fel...@pengutronix.de> > --- > drivers/clk/imx/clk-imx8mm.c | 65 ++++++++++++++++++------------------ > 1 file changed, 33 insertions(+), 32 deletions(-)
Applied, thanks Sascha > > diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c > index e6927f58f4..d467062e64 100644 > --- a/drivers/clk/imx/clk-imx8mm.c > +++ b/drivers/clk/imx/clk-imx8mm.c > @@ -280,6 +280,7 @@ static int imx8mm_clocks_init(struct device_node *ccm_np) > { > struct device_node *anatop_np; > void __iomem *ccm, *ana; > + u32 val; > int ret; > > anatop_np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop"); > @@ -340,45 +341,45 @@ static int imx8mm_clocks_init(struct device_node > *ccm_np) > clks[IMX8MM_SYS_PLL3_OUT] = imx_clk_gate("sys_pll3_out", > "sys_pll3_bypass", ana + 0x114, 11); > > /* SYS PLL1 fixed output */ > - clks[IMX8MM_SYS_PLL1_40M_CG] = imx_clk_gate("sys_pll1_40m_cg", > "sys_pll1", ana + 0x94, 27); > - clks[IMX8MM_SYS_PLL1_80M_CG] = imx_clk_gate("sys_pll1_80m_cg", > "sys_pll1", ana + 0x94, 25); > - clks[IMX8MM_SYS_PLL1_100M_CG] = imx_clk_gate("sys_pll1_100m_cg", > "sys_pll1", ana + 0x94, 23); > - clks[IMX8MM_SYS_PLL1_133M_CG] = imx_clk_gate("sys_pll1_133m_cg", > "sys_pll1", ana + 0x94, 21); > - clks[IMX8MM_SYS_PLL1_160M_CG] = imx_clk_gate("sys_pll1_160m_cg", > "sys_pll1", ana + 0x94, 19); > - clks[IMX8MM_SYS_PLL1_200M_CG] = imx_clk_gate("sys_pll1_200m_cg", > "sys_pll1", ana + 0x94, 17); > - clks[IMX8MM_SYS_PLL1_266M_CG] = imx_clk_gate("sys_pll1_266m_cg", > "sys_pll1", ana + 0x94, 15); > - clks[IMX8MM_SYS_PLL1_400M_CG] = imx_clk_gate("sys_pll1_400m_cg", > "sys_pll1", ana + 0x94, 13); > + /* > + * The gates in CCM_ANALOG_SYS_PLL1_GEN_CTRL are not handled by the > + * driver, make sure they are all enabled. > + */ > + val = readl(ana + 0x94); > + val |= BIT(13) | BIT(15) | BIT(17) | BIT(19) | BIT(21) | BIT(23) | > BIT(25) | BIT(27); > + writel(val, ana + 0x94); > + > clks[IMX8MM_SYS_PLL1_OUT] = imx_clk_gate("sys_pll1_out", "sys_pll1", > ana + 0x94, 11); > > - clks[IMX8MM_SYS_PLL1_40M] = imx_clk_fixed_factor("sys_pll1_40m", > "sys_pll1_40m_cg", 1, 20); > - clks[IMX8MM_SYS_PLL1_80M] = imx_clk_fixed_factor("sys_pll1_80m", > "sys_pll1_80m_cg", 1, 10); > - clks[IMX8MM_SYS_PLL1_100M] = imx_clk_fixed_factor("sys_pll1_100m", > "sys_pll1_100m_cg", 1, 8); > - clks[IMX8MM_SYS_PLL1_133M] = imx_clk_fixed_factor("sys_pll1_133m", > "sys_pll1_133m_cg", 1, 6); > - clks[IMX8MM_SYS_PLL1_160M] = imx_clk_fixed_factor("sys_pll1_160m", > "sys_pll1_160m_cg", 1, 5); > - clks[IMX8MM_SYS_PLL1_200M] = imx_clk_fixed_factor("sys_pll1_200m", > "sys_pll1_200m_cg", 1, 4); > - clks[IMX8MM_SYS_PLL1_266M] = imx_clk_fixed_factor("sys_pll1_266m", > "sys_pll1_266m_cg", 1, 3); > - clks[IMX8MM_SYS_PLL1_400M] = imx_clk_fixed_factor("sys_pll1_400m", > "sys_pll1_400m_cg", 1, 2); > + clks[IMX8MM_SYS_PLL1_40M] = imx_clk_fixed_factor("sys_pll1_40m", > "sys_pll1_out", 1, 20); > + clks[IMX8MM_SYS_PLL1_80M] = imx_clk_fixed_factor("sys_pll1_80m", > "sys_pll1_out", 1, 10); > + clks[IMX8MM_SYS_PLL1_100M] = imx_clk_fixed_factor("sys_pll1_100m", > "sys_pll1_out", 1, 8); > + clks[IMX8MM_SYS_PLL1_133M] = imx_clk_fixed_factor("sys_pll1_133m", > "sys_pll1_out", 1, 6); > + clks[IMX8MM_SYS_PLL1_160M] = imx_clk_fixed_factor("sys_pll1_160m", > "sys_pll1_out", 1, 5); > + clks[IMX8MM_SYS_PLL1_200M] = imx_clk_fixed_factor("sys_pll1_200m", > "sys_pll1_out", 1, 4); > + clks[IMX8MM_SYS_PLL1_266M] = imx_clk_fixed_factor("sys_pll1_266m", > "sys_pll1_out", 1, 3); > + clks[IMX8MM_SYS_PLL1_400M] = imx_clk_fixed_factor("sys_pll1_400m", > "sys_pll1_out", 1, 2); > clks[IMX8MM_SYS_PLL1_800M] = imx_clk_fixed_factor("sys_pll1_800m", > "sys_pll1_out", 1, 1); > > /* SYS PLL2 fixed output */ > - clks[IMX8MM_SYS_PLL2_50M_CG] = imx_clk_gate("sys_pll2_50m_cg", > "sys_pll2", ana + 0x104, 27); > - clks[IMX8MM_SYS_PLL2_100M_CG] = imx_clk_gate("sys_pll2_100m_cg", > "sys_pll2", ana + 0x104, 25); > - clks[IMX8MM_SYS_PLL2_125M_CG] = imx_clk_gate("sys_pll2_125m_cg", > "sys_pll2", ana + 0x104, 23); > - clks[IMX8MM_SYS_PLL2_166M_CG] = imx_clk_gate("sys_pll2_166m_cg", > "sys_pll2", ana + 0x104, 21); > - clks[IMX8MM_SYS_PLL2_200M_CG] = imx_clk_gate("sys_pll2_200m_cg", > "sys_pll2", ana + 0x104, 19); > - clks[IMX8MM_SYS_PLL2_250M_CG] = imx_clk_gate("sys_pll2_250m_cg", > "sys_pll2", ana + 0x104, 17); > - clks[IMX8MM_SYS_PLL2_333M_CG] = imx_clk_gate("sys_pll2_333m_cg", > "sys_pll2", ana + 0x104, 15); > - clks[IMX8MM_SYS_PLL2_500M_CG] = imx_clk_gate("sys_pll2_500m_cg", > "sys_pll2", ana + 0x104, 13); > + /* > + * The gates in CCM_ANALOG_SYS_PLL2_GEN_CTRL are not handled by the > + * driver, make sure they are all enabled. > + */ > + val = readl(ana + 0x104); > + val |= BIT(13) | BIT(15) | BIT(17) | BIT(19) | BIT(21) | BIT(23) | > BIT(25) | BIT(27); > + writel(val, ana + 0x104); > + > clks[IMX8MM_SYS_PLL2_OUT] = imx_clk_gate("sys_pll2_out", "sys_pll2", > ana + 0x104, 11); > > - clks[IMX8MM_SYS_PLL2_50M] = imx_clk_fixed_factor("sys_pll2_50m", > "sys_pll2_50m_cg", 1, 20); > - clks[IMX8MM_SYS_PLL2_100M] = imx_clk_fixed_factor("sys_pll2_100m", > "sys_pll2_100m_cg", 1, 10); > - clks[IMX8MM_SYS_PLL2_125M] = imx_clk_fixed_factor("sys_pll2_125m", > "sys_pll2_125m_cg", 1, 8); > - clks[IMX8MM_SYS_PLL2_166M] = imx_clk_fixed_factor("sys_pll2_166m", > "sys_pll2_166m_cg", 1, 6); > - clks[IMX8MM_SYS_PLL2_200M] = imx_clk_fixed_factor("sys_pll2_200m", > "sys_pll2_200m_cg", 1, 5); > - clks[IMX8MM_SYS_PLL2_250M] = imx_clk_fixed_factor("sys_pll2_250m", > "sys_pll2_250m_cg", 1, 4); > - clks[IMX8MM_SYS_PLL2_333M] = imx_clk_fixed_factor("sys_pll2_333m", > "sys_pll2_333m_cg", 1, 3); > - clks[IMX8MM_SYS_PLL2_500M] = imx_clk_fixed_factor("sys_pll2_500m", > "sys_pll2_500m_cg", 1, 2); > + clks[IMX8MM_SYS_PLL2_50M] = imx_clk_fixed_factor("sys_pll2_50m", > "sys_pll2_out", 1, 20); > + clks[IMX8MM_SYS_PLL2_100M] = imx_clk_fixed_factor("sys_pll2_100m", > "sys_pll2_out", 1, 10); > + clks[IMX8MM_SYS_PLL2_125M] = imx_clk_fixed_factor("sys_pll2_125m", > "sys_pll2_out", 1, 8); > + clks[IMX8MM_SYS_PLL2_166M] = imx_clk_fixed_factor("sys_pll2_166m", > "sys_pll2_out", 1, 6); > + clks[IMX8MM_SYS_PLL2_200M] = imx_clk_fixed_factor("sys_pll2_200m", > "sys_pll2_out", 1, 5); > + clks[IMX8MM_SYS_PLL2_250M] = imx_clk_fixed_factor("sys_pll2_250m", > "sys_pll2_out", 1, 4); > + clks[IMX8MM_SYS_PLL2_333M] = imx_clk_fixed_factor("sys_pll2_333m", > "sys_pll2_out", 1, 3); > + clks[IMX8MM_SYS_PLL2_500M] = imx_clk_fixed_factor("sys_pll2_500m", > "sys_pll2_out", 1, 2); > clks[IMX8MM_SYS_PLL2_1000M] = imx_clk_fixed_factor("sys_pll2_1000m", > "sys_pll2_out", 1, 1); > > /* Core Slice */ > -- > 2.30.2 > > > -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |