[PATCH 10/10] RFC: ARM: dts: i.MX8MM: describe standlone feature controller

[Ahmad Fatoum]

Now with i.MX8M feature controller driver support available, define it
for the i.MX8MM to ensure the kernel DT does not attempt accessing VPUs
and their power domain/blkctrl if barebox knows them to be unavailable.

This is needed because the upstream kernel imx8mm.dtsi only describes
the full-featured SoC, which can lead to hangs when instantiating
drivers for hardware that's unavailable in a less-featureful variant of
the SoC.

[afa: This is one possibility for the binding. My favourite would
 be having the ocotp be the feature-controller, see previous commits]

Signed-off-by: Ahmad Fatoum <a.fat...@pengutronix.de>
---
 arch/arm/dts/imx8mm.dtsi | 61 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 61 insertions(+)

diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi
index cdf212820594..bef791739e72 100644
--- a/arch/arm/dts/imx8mm.dtsi
+++ b/arch/arm/dts/imx8mm.dtsi
@@ -1,8 +1,25 @@
 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include <dt-bindings/features/imx8m.h>
+
 / {
        aliases {
                gpr.reboot_mode = &reboot_mode_gpr;
        };
+
+       feat: imx8m-feature-controller {
+               compatible = "barebox,imx8mm-featctrl";
+               #feature-cells = <1>;
+               barebox,feature-controller;
+               nvmem-cell-names = "tester4";
+               nvmem-cells = <&soc_tester4>;
+       };
+};
+
+&ocotp {
+       soc_tester4: tester4@14 {
+               reg = <0x14 4>;
+       };
 };
 
 &pgc_otg1 {
@@ -24,3 +41,47 @@
                mode-serial = <0x00000010>, <0x40000000>;
        };
 };
+
+&A53_1 {
+       barebox,feature-gates = <&feat IMX8M_FEAT_CPU_DUAL>;
+};
+
+&A53_2 {
+       barebox,feature-gates = <&feat IMX8M_FEAT_CPU_QUAD>;
+};
+
+&A53_3 {
+       barebox,feature-gates = <&feat IMX8M_FEAT_CPU_QUAD>;
+};
+
+&gpc {
+       barebox,feature-gates = <&feat 0>;
+};
+
+&vpu_g1 {
+       barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
+};
+
+&vpu_g2 {
+       barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
+};
+
+&vpu_blk_ctrl {
+       barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
+};
+
+&pgc_vpumix {
+       barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
+};
+
+&pgc_vpu_g1 {
+       barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
+};
+
+&pgc_vpu_g2 {
+       barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
+};
+
+&pgc_vpu_h1 {
+       barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
+};
-- 
2.30.2