[PATCH v2 04/11] RISC-V: StarFive: J7100: set /soc/dma-noncoherent

[Ahmad Fatoum]

With upcoming changes, cache handling will be skipped on RISC-V, because
arch is cache-coherent by default. StarFive JH7100 has non-coherent DMA
masters though, so note that in the DT.

Signed-off-by: Ahmad Fatoum <a.fat...@pengutronix.de>
---
v1 -> v2:
  - no change
---
 arch/riscv/Kconfig.socs    | 1 +
 arch/riscv/dts/jh7100.dtsi | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 56ba5ecf5865..cef9cd52300c 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -88,6 +88,7 @@ config SOC_STARFIVE_JH7100
        bool
        select SOC_STARFIVE_JH71XX
        select SIFIVE_L2
+       select OF_DMA_COHERENCY
        help
          Unlike JH7110 and later, CPU on the JH7100 are not cache-coherent
          with respect to DMA masters like GMAC and DW MMC controller.
diff --git a/arch/riscv/dts/jh7100.dtsi b/arch/riscv/dts/jh7100.dtsi
index e3990582af97..b11801553bf7 100644
--- a/arch/riscv/dts/jh7100.dtsi
+++ b/arch/riscv/dts/jh7100.dtsi
@@ -212,6 +212,7 @@ soc {
                #clock-cells = <1>;
                compatible = "simple-bus";
                ranges;
+               dma-noncoherent;
 
                intram0: sram@18000000 {
                        compatible = "mmio-sram";
-- 
2.39.2