On Tue, 06 Feb 2024 21:37:47 -0500, Thaison Phan wrote:
> The aarch64 bootm image handler for barebox can choose a load address
> that is not 4KB aligned. This can result in unexpected behavior with
> the ADRP instruction that is available in 64 bit ARM architectures.
> ADRP forms a PC-relative address to a 4KB page where the bottom 12
> bits of the current PC will be masked out. When the load address of
> the barebox image is not 4KB aligned ADRP can end up forming an
> address that starts from an invalid page of memory or the wrong page
> of memory that was expected to be formed. The following patch aligns
> the load address for the next barebox image to be 4KB aligned to
> accommodate the ADRP instruction.
>
> [...]
Applied, thanks!
[1/1] Patch to fix bootm barebox load address alignment to acomodate ADRP
instruction
https://git.pengutronix.de/cgit/barebox/commit/?id=af694bdae717 (link may
not be stable)
Best regards,
--
Sascha Hauer <s.ha...@pengutronix.de>
