The isw handoff registers are free to use for the bootloader. Add their offsets for lowlevel debugging purposes.
Signed-off-by: Steffen Trumtrar <s.trumt...@pengutronix.de> --- include/mach/socfpga/arria10-system-manager.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/mach/socfpga/arria10-system-manager.h b/include/mach/socfpga/arria10-system-manager.h index f92025ae32..536baf6bc3 100644 --- a/include/mach/socfpga/arria10-system-manager.h +++ b/include/mach/socfpga/arria10-system-manager.h @@ -53,6 +53,15 @@ #define ARRIA10_SYSMGR_FPGA2SOC_CTRL (ARRIA10_SYSMGR_ADDR + 0xd8) #define ARRIA10_SYSMGR_ROM_INITSWLASTLD (ARRIA10_SYSMGR_ADDR + 0x10) +#define ARRIA10_SYSMGR_ROM_ISW0 (ARRIA10_SYSMGR_ADDR + 0x230) +#define ARRIA10_SYSMGR_ROM_ISW1 (ARRIA10_SYSMGR_ADDR + 0x234) +#define ARRIA10_SYSMGR_ROM_ISW2 (ARRIA10_SYSMGR_ADDR + 0x238) +#define ARRIA10_SYSMGR_ROM_ISW3 (ARRIA10_SYSMGR_ADDR + 0x23c) +#define ARRIA10_SYSMGR_ROM_ISW4 (ARRIA10_SYSMGR_ADDR + 0x240) +#define ARRIA10_SYSMGR_ROM_ISW5 (ARRIA10_SYSMGR_ADDR + 0x244) +#define ARRIA10_SYSMGR_ROM_ISW6 (ARRIA10_SYSMGR_ADDR + 0x248) +#define ARRIA10_SYSMGR_ROM_ISW7 (ARRIA10_SYSMGR_ADDR + 0x24c) + #define ARRIA10_SYSMGR_BOOTINFO_BSEL_MASK 0x00007000 -- 2.43.2
