Hello Ahmad, This has been a while that I asked you about a question on the PCIE for the LS1021A. We are developing a new product with a NVME device using the LS1021A CPU and I would like to add LPAE support to barebox so that PCI child devices can be probed.
I am trying to figure out how to assemble LPAE support based on the information you gave me below and what I see in U-boot. A grep of LPAE in U-boot shows several files with specific code for LPAE: arch/arm/cpu/armv7/start.S arch/arm/lib/cache-cp15.c arch/arm/cpu/armv7/ls102xa/cpu.c I do recognize similar pieces of code between barebox and U-boot From the message below, I understand I would need to update map_io_sections to map the PCI address as in U-boot mmu_setup from the file arch/arm/cpu/armv7/ls102xa/cpu.c Cheers, Renaud > -----Original Message----- > From: Ahmad Fatoum <[email protected]> > Sent: 09 December 2022 19:18 > To: Renaud Barbier <[email protected]>; Barebox List > <[email protected]> > Cc: Lucas Stach <[email protected]> > Subject: Re: PCIE on LS1021A > > ***NOTICE*** This came from an external source. Use caution when > replying, clicking links, or opening attachments. > > On 09.12.22 19:37, Ahmad Fatoum wrote: > >> From my debugging I can see that the Layerscape PCIE driver use VA > >> address = PA address = 0x24000000 > >> > >> So Is the problem I am seeing an issue with mapping the correct physical > address for a 32-bit processor? > >> > >> If yes, how can I map the 64-bit PA to a 32-bit VA? > > > > Normally, you would call map_io_sections as pci-tegra does, but in > > your case this alone is insufficient as you will need to implement > > ARM32 LPAE support first. Once that's in place, you can use > > map_io_sections and map it to e.g. 0x24000000 as U-Boot does > arch/arm/cpu/armv7/ls102xa/cpu.c mmu_setup(). > > > > U-Boot LPAE support was added to support Rpi2, which starts in HYP > > mode, but we had worked around that in barebox to not require LPAE. > > For your case however, I don't believe there's a way around using LPAE > page tables. > > > > Tangentially related: I don't know how the PCI controller maintains > > cache coherency, but if it does write back through CPU caches, you may > observe memory corruption. > > > > It may be the safest for you to disable cache snooping for PCIe until > > that's resolved (We've this planned, but it will probably not happen this > year. > > If you're interested I can elaborate). > > I should have shortened the context a bit. Posting again in case you missed > it. > > > > > Cheers, > > Ahmad > > > > > > > >> > >> Cheers, > >> Renaud > >> > >> > >> > >> > >> > > > > -- > Pengutronix e.K. | | > Steuerwalder Str. 21 | > https://urldefense.com/v3/__http://www.pengutronix.de/__;!!HKOSU0g!CfA > u4L9MQvIuEvfQmVymcZYkrdbrn98J2QbYMFsHhqFrxp8fDzjT6- > h9nSajsgYcNvsCjJVWd98oYvdyj7pvR-ZfDY0$ | > 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
