From: Alexander Shiyan <[email protected]> At least one RK3588 clock (CPLL) uses 1.5 GHz, so let's add that frequency to the PLL table. This change is taken from the mainline Linux kernel.
Signed-off-by: Alexander Shiyan <[email protected]> Link: https://lore.barebox.org/[email protected] Signed-off-by: Sascha Hauer <[email protected]> (cherry picked from commit dc780c20b06749773dfc38e177957beae14960ab) Signed-off-by: Ahmad Fatoum <[email protected]> --- drivers/clk/rockchip/clk-rk3588.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c index f6d16ed0cf30..5aecfb3b1b71 100644 --- a/drivers/clk/rockchip/clk-rk3588.c +++ b/drivers/clk/rockchip/clk-rk3588.c @@ -88,6 +88,7 @@ static struct rockchip_pll_rate_table rk3588_pll_rates[] = { RK3588_PLL_RATE(1560000000, 2, 260, 1, 0), RK3588_PLL_RATE(1536000000, 2, 256, 1, 0), RK3588_PLL_RATE(1512000000, 2, 252, 1, 0), + RK3588_PLL_RATE(1500000000, 2, 250, 1, 0), RK3588_PLL_RATE(1488000000, 2, 248, 1, 0), RK3588_PLL_RATE(1464000000, 2, 244, 1, 0), RK3588_PLL_RATE(1440000000, 2, 240, 1, 0), -- 2.47.3
