On Agilex 5, barebox runs in the HPS (hard processor system) which needs to explicitly request QSPI flash access from the SDM (secure device manager). This request may be denied by the SDM. Furthermore, barebox needs to store the clock rate reported by the SDM.
Cleanup and refactor the code that handles the QSPI flash request from the SDM. This is a preparation for eventually reading a second stage boot loader from QSPI flash. Signed-off-by: Michael Tretter <[email protected]> --- Michael Tretter (6): arm: socfpga: agilex5: add missing include soc64-regs.h arm: socfgpa: agilex5: remove mailbox_s10 from barebox proper arm: socfpga: agilex5: extract function to request qspi access arm: socfpga: mailbox_s10: keep clock rate in Hz arm: socfpga: mailbox_s10: add write_qspi_refclk helper arm: socfpga: agilex5: extract write_qspi_refclk from mailbox arch/arm/mach-socfpga/Makefile | 1 - arch/arm/mach-socfpga/atf.c | 27 +++++++++++++++++++++++++-- arch/arm/mach-socfpga/mailbox_s10.c | 23 ++++++++--------------- include/mach/socfpga/mailbox_s10.h | 2 +- include/mach/socfpga/soc64-firewall.h | 2 ++ include/mach/socfpga/soc64-system-manager.h | 21 +++++++++++++++++++++ 6 files changed, 57 insertions(+), 19 deletions(-) --- base-commit: 7a178f01f6e25474a5eb6e071ca479076b8d4d92 change-id: 20260505-socfpga-agilex5-qspi-5cb9abd175a8 Best regards, -- Michael Tretter <[email protected]>
