On Monday, March 9, 2015 at 1:22:09 PM UTC-4, RobertCNelson wrote:
> I've been seeing that locally too, but i see the issue...
>
> CONFIG_SERIAL_8250_NR_UARTS=4
> CONFIG_SERIAL_8250_RUNTIME_UARTS=4
>
>
One other thing I noticed, I see entries in dmesg output like this:
[ 2.656184] bone-pinmux-helper P8_37_pinmux.28: Set initial pinmux mode
to uart
[ 2.656791] bone-pinmux-helper P8_38_pinmux.29: Set initial pinmux mode
to uart
In fact, I see it for the ttyO1, ttyO2, ttyO4 and ttyO5 TXD and RXD pins.
However, I want to enable hardware flow control (CTS/RTS) for ttyO4 and
ttyO5, so I have added the following lines to my custom .dts file:
P8_33_pinmux {
mode = "uart";
};
P8_35_pinmux {
mode = "uart";
};
P8_31_pinmux {
mode = "uart";
};
P8_32_pinmux {
mode = "uart";
};
But I don't see corresponding entries in `dmsg` showing the
bone-pinmux-helper settings the uart modes for 3 of these extra pins (it
did actually set the uart mode for P8_31). A bit of digging in
am335x-bone-common-pinmux.dtsi shows that it's missing the pinctrl modes
for P8_32, P8_33 and P8_35, along with the uart pinmux definitions for
P8_33 and P8_35. So I added them and I now see bone-pinmux-helper property
configuring these pins. Here's the diff for am335x-bone-common-pinmux.dtsi:
Next up, I need to get or build a kernel with 5 serial ports enabled to
test this.
-W
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diff --git a/src/arm/am335x-bone-common-pinmux.dtsi b/src/arm/am335x-bone-common-pinmux.dtsi
index 7c7ea61..75c61a7 100644
--- a/src/arm/am335x-bone-common-pinmux.dtsi
+++ b/src/arm/am335x-bone-common-pinmux.dtsi
@@ -747,6 +747,8 @@
pinctrl-single,pins = <0x0d4 0x37>; }; /* Mode 7, Pull-Up, RxActive */
P8_33_gpio_pd_pin: pinmux_P8_33_gpio_pd_pin {
pinctrl-single,pins = <0x0d4 0x27>; }; /* Mode 7, Pull-Down, RxActive */
+ P8_33_uart_pin: pinmux_P8_33_uart_pin {
+ pinctrl-single,pins = <0x0d4 0x06>; }; /* Mode 6, Pull-Down */
P8_33_hdmi_pin: pinmux_P8_33_hdmi_pin {
pinctrl-single,pins = <0x0d4 0x08>; }; /* lcd_data13.lcd_data13, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
@@ -773,6 +775,8 @@
pinctrl-single,pins = <0x0d0 0x37>; }; /* Mode 7, Pull-Up, RxActive */
P8_35_gpio_pd_pin: pinmux_P8_35_gpio_pd_pin {
pinctrl-single,pins = <0x0d0 0x27>; }; /* Mode 7, Pull-Down, RxActive */
+ P8_35_uart_pin: pinmux_P8_35_uart_pin {
+ pinctrl-single,pins = <0x0d0 0x26>; }; /* Mode 6, Pull-Down, RxActive */
P8_35_hdmi_pin: pinmux_P8_35_hdmi_pin {
pinctrl-single,pins = <0x0d0 0x08>; }; /* lcd_data12.lcd_data12, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
@@ -1621,23 +1625,25 @@
P8_32_pinmux {
compatible = "bone-pinmux-helper";
status = "okay";
- pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "hdmi";
+ pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "uart", "hdmi";
pinctrl-0 = <&P8_32_default_pin>;
pinctrl-1 = <&P8_32_gpio_pin>;
pinctrl-2 = <&P8_32_gpio_pu_pin>;
pinctrl-3 = <&P8_32_gpio_pd_pin>;
- pinctrl-4 = <&P8_32_hdmi_pin>;
+ pinctrl-4 = <&P8_32_uart_pin>;
+ pinctrl-5 = <&P8_32_hdmi_pin>;
};
P8_33_pinmux {
compatible = "bone-pinmux-helper";
status = "okay";
- pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "hdmi";
+ pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "uart", "hdmi";
pinctrl-0 = <&P8_33_default_pin>;
pinctrl-1 = <&P8_33_gpio_pin>;
pinctrl-2 = <&P8_33_gpio_pu_pin>;
pinctrl-3 = <&P8_33_gpio_pd_pin>;
- pinctrl-4 = <&P8_33_hdmi_pin>;
+ pinctrl-4 = <&P8_33_uart_pin>;
+ pinctrl-5 = <&P8_33_hdmi_pin>;
};
P8_34_pinmux {
@@ -1655,12 +1661,13 @@
P8_35_pinmux {
compatible = "bone-pinmux-helper";
status = "okay";
- pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "hdmi";
+ pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "uart", "hdmi";
pinctrl-0 = <&P8_35_default_pin>;
pinctrl-1 = <&P8_35_gpio_pin>;
pinctrl-2 = <&P8_35_gpio_pu_pin>;
pinctrl-3 = <&P8_35_gpio_pd_pin>;
- pinctrl-4 = <&P8_35_hdmi_pin>;
+ pinctrl-4 = <&P8_35_uart_pin>;
+ pinctrl-5 = <&P8_35_hdmi_pin>;
};
P8_36_pinmux {
