The starting point for my questions is the BB-SPIDEV0-00A0.dts
<https://github.com/jadonk/cape-firmware/blob/master/arch/arm/boot/dts/BB-SPIDEV0-00A0.dts>
.
*1. Description of problem:*
The following fragment was taken from the above device tree spec:
fragment@0 {
target = <&am33xx_pinmux>;
__overlay__ {
/* default state has all gpios released and mode set to uart1 */
bb_spi0_pins: pinmux_bb_spi0_pins {
pinctrl-single,pins = <
0x150 0x30 /* spi0_sclk.spi0_sclk, INPUT_PULLUP | MODE0 */
0x154 0x30 /* spi0_d0.spi0_d0, INPUT_PULLUP | MODE0 */
0x158 0x10 /* spi0_d1.spi0_d1, OUTPUT_PULLUP | MODE0 */
0x15c 0x10 /* spi0_cs0.spi0_cs0, OUTPUT_PULLUP | MODE0 */
>;
};
};
};
The fragment configures the P9.17, P9.18, P9.21, P9.22 pins to Mode 0 for
the SPI driver. I'm also aware of the table P9 Header
<https://github.com/derekmolloy/boneDeviceTree/blob/master/docs/BeagleboneBlackP9HeaderTable.pdf>
table
with the offset addresses of the pins and the AM335x Sitara Processors
Technical Reference Manual (Rev. M)
<http://www.ti.com/dsp/docs/dspsupporttechdocs.tsp?sectionId=3&tabId=409&docCategoryId=6&viewType=mostuseful&rootFamilyId=44&familyId=2920>
with
information on how to configure the CPU registers.
My problem is that the addresses in the device tree fragment above do not
match the addresses in the Reference Manual.
In the fragment above the offset addresses are: 0x150, 0x154, 0x158 and
0x15c. In the Reference Manual Chapter 9.3 page 1372 the offset addresses
are: 0x950, 0x954, 0x958, 0x95c.
*Question:* Can someone help me understand where are the addresses from the
fragment taken/obtained/calculated from?
*2. Description of problem*
The following fragments were taken from the above device tree specification:
...
fragment@0 {
target = <&am33xx_pinmux>;
__overlay__ {
...
...
fragment@1 {
target = <&spi0>; /* spi0 is numbered correctly */
__overlay__ {
...
I could not find on the web what is the functionality of the *target* property
in a device tree. I'm somehow familiar with the aliases concept. So I think
&am33xx_pinmux and &spi0 are aliases for "something". However there is
nothing defined in the device tree specification above.
*Questions:*
What is the functionality/role of the *target* property? Where are the
&am33xx_pinmux and &spi0 defined and what do they mean?
I would also appreciate some links/references if available, so I can
further read.
I'm also interested if there is a list with all the aliases for BeagleBone
Black.
--
For more options, visit http://beagleboard.org/discuss
---
You received this message because you are subscribed to the Google Groups
"BeagleBoard" group.
To unsubscribe from this group and stop receiving emails from it, send an email
to beagleboard+unsubscr...@googlegroups.com.
To view this discussion on the web visit
https://groups.google.com/d/msgid/beagleboard/ef25f5e9-d3b2-4ce3-823a-adf9b4833804%40googlegroups.com.
For more options, visit https://groups.google.com/d/optout.
