Justin:

>From your questions, you seemed to have an over-simplified view as to how
the clocks are generated in the Sitara.

It is not your grandfather's PIC.

It is a very modern, sophisticated, clock system, with many of the clock
subsystems being variable rate.

A "Clock Tree" is the generic term for the way all of the internal clocks
are generated. If you draw a block diagram, it starts to look like a tree
that branches out from the trunk and lots of the branches have more
branches.

Just because they are derived from a single (24 MHz) clock source, does not
mean that they are synchronous, or even have a constant relationship.  Lots
of them are variable rate, such as the CPU, and almost all of the
communications peripherals.  And then everything is complicated by low
power modes and sleep modes.

The PRU main clock does appear to be a constant 200 MHz.

If you want to dig into the details, they are covered in the "AM335x
Technical Reference Manual".

What I call the clock tree is page 1136, Figure 8-10.  Detail on the
branches follows on the next ten pages.

--- Graham

==




On Sun, Apr 30, 2017 at 8:42 AM, 'Roberts Maria' via BeagleBoard <
beagleboard@googlegroups.com> wrote:

>
> --------------------------------------------
> On Sun, 4/30/17,  <dinu...@gmail.com> wrote:
>
>  Subject: Re: [beagleboard] Re: PRU and CPU driven by different
> oscillators?
>  To: "BeagleBoard" <beagleboard@googlegroups.com>
>  Date: Sunday, April 30, 2017, 2:31 PM
>
>  You may
>  find this tool from TI
>  useful: http://processors.wiki.ti.com/index.php/AM335x_Clock_Tree_Tool
>
>  On Saturday, April 29, 2017 at
>  10:14:31 PM UTC+3, Justin Pearson wrote:Thanks Graham. What
>  do you mean by "check and verify the clock tree
>  behavior"? I searched the TRM for "clock
>  tree" but I'm still not sure how to figure out
>  which timers make their way through various PLLs to the PRU
>  and main CPU.
>
>
>  On Wed, Apr 26, 2017 at
>  10:00 AM, Graham <gra...@flex-radio.com> wrote:
>  Well, best way is to
>  read the schematic. (BBB Rev C schematic, dated March 21,
>  2014)24 MHz Sitara clock crystal is on upper left of
>  page 3, hooked to main oscillator I/O.There is
>  also a 32 kHz crystal shown there for the Real Time
>  Clock.
>  The 25 MHz
>  crystal is on page 9, hooked to the LAN8710, which is the
>  Ethernet PHI.
>  I am not
>  a PRU expert, but I don't think there is, or should be,
>  a fixed relationship betweenthe PRU clock and the
>  CPU clock.  The CPU in a Sitara is a variable speed CPU,
>  and can run anywhere from a few hundred MHz to a
>  GHz, depending on loading,and it is under kernel
>  control.
>  I would not
>  think you would want the 200 MHz clock for the PRU to be
>  variablelike that, since it would totally destroy
>  the real time advantage of the PRU.
>  So, I suspect that the clock for the
>  PRU is a fixed clock coming from a differentplace
>  in the clock tree than the variable speed CPU.
>  You should really check and verify
>  the clock tree behavior.
>  --- Graham
>  ==
>  On Wednesday, April 26, 2017 at 8:02:38 AM
>  UTC-5, Justin Pearson wrote:Thanks Graham.
>  Follow-up questions:
>  1.
>  Where exactly did you find this information? I looked
>  through the TRM and SRM but couldn't find anything
>  definitive.
>  2. Is the
>  200-MHz PRU driven from the same 24 MHz oscillator that
>  drives the CPU? If so, is it correct that the PRU cycle
>  counter increments precisely once for every 5 CPU
>  cycles?
>  Thanks for
>  your help.-Justin
>
>  On Tuesday, April 25, 2017 at 7:35:19 PM UTC-7,
>  Graham wrote:The CPU in a BBB
>  runs from a 24 MHz Oscillator.There is a 25 MHz
>  oscillator on the board, but that is for the
>  Ethernet.--- Graham
>  ==
>
>  On Tuesday, April 25, 2017 at 7:09:50 PM UTC-5,
>  Justin Pearson wrote:How can I find out
>  whether the PRU and CPU are driven by the same oscillator?
>  Specifically, a colleague told me that the IEP timer (which
>  I'm reading with the PRU) is driven by a 24 MHz
>  oscillator that's PLL'd so the timer increments at
>  200 MHz, whereas the CPU is driven by a 25 MHz oscillator
>  PLL'd so that the CPU runs at 1 GHz.
>  It seems to me that if they're
>  driven by different oscillators, then they could drift apart
>  over time.
>
>  Page 1177 of the TRM (spruh73n.pdf)
>  mentions a 32-kHz crystal oscillator, but I don't see
>  how that's related.
>  Also, are these oscillators within
>  the Sitara SoC, or somewhere else on the BBB? The SRM just
>  references 24.576 MHz oscillator (pg 70 of e14 BBB_SRM_rev
>  0.9.pdf), and I'm not sure how that's related to the
>  24/25 MHz oscillators my colleague
>  mentioned.
>  Thanks for your help.
>
>
>
>
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