You might help your self by explaining why you might want to do this. In other words, what is the problem you are trying to solve.
Since 24 MHz is the master clock for the CPU, changing it will break all the timing systems, time, serial ports, anything using or depending on time or frequency. And since there are internal PLLs in the Sitara, there are limits as to how far you can move. You might be better off designing a little hardware circuit that would take 12.8 as an input and provide a phase locked 24 MHz as an output. Or leaving the master clock on the Sitara alone, and learning how to move data across clock domain boundaries. --- Graham == On Saturday, December 9, 2017 at 7:00:08 AM UTC-6, ansari...@gmail.com wrote: > > Dear All, > Pls suggest me how to clock externally by OCXO 12.80001 MHz by > replacing Y2=24 MHz. > Also suggest what actions will be required in > uboot/kernel/userspace...etc... > > Thanks > Ansari. > -- For more options, visit http://beagleboard.org/discuss --- You received this message because you are subscribed to the Google Groups "BeagleBoard" group. To unsubscribe from this group and stop receiving emails from it, send an email to beagleboard+unsubscr...@googlegroups.com. To view this discussion on the web visit https://groups.google.com/d/msgid/beagleboard/96758bbe-9727-4ff1-8805-8ff9b7c2677e%40googlegroups.com. For more options, visit https://groups.google.com/d/optout.
