DDR bandwidth will be sufficient. You should be worried about DDR read access latency. I think that in the worst case you may not be able to read data in time for the spi byte shift. I would suggest to dedicate one pru to copy from ddr into shared sram. Or check if hw spi can ne used in slave mode.
TI wiki had a table with typical cycles needed by pru for accessing ddr and sram. Regards, Dimitar понеделник, 22 януари 2018 г., 18:58:17 UTC+2, David Edwards написа: > > I'm also reading that allocating more than 8MB of the external RAM may be > an issue. Looks like I might need the core after all to facilitate an > intermediary ring buffer to the full 30MB of memory is user space.... > -- For more options, visit http://beagleboard.org/discuss --- You received this message because you are subscribed to the Google Groups "BeagleBoard" group. To unsubscribe from this group and stop receiving emails from it, send an email to beagleboard+unsubscr...@googlegroups.com. To view this discussion on the web visit https://groups.google.com/d/msgid/beagleboard/ef29a7e1-59a5-4a05-b695-4e6f7c737ca0%40googlegroups.com. For more options, visit https://groups.google.com/d/optout.
