With a sample size of one, r31 appears to be 4 instructions behind the state of the pin.
On Thursday, February 25, 2021 at 12:26:16 PM UTC-5 Paul Beam wrote: > I am, unfortunately, bit-banging SPI with the PRU, and I seem to be > running into a speed limit < 50 MHz I desire. I can certainly create a > clock that fast, but reading data seems to be delayed. I can see on the > logic analyzer a "0" clearly being read as a '1" so there is either a delay > in my clock output or a delay in my input or both. I would like to think > that r30 and r31 are tied directly to the outside world, but now I am > thinking there is something in between that is either clocked or just has > significant output delays. Anyone else encountered this? -- For more options, visit http://beagleboard.org/discuss --- You received this message because you are subscribed to the Google Groups "BeagleBoard" group. To unsubscribe from this group and stop receiving emails from it, send an email to beagleboard+unsubscr...@googlegroups.com. To view this discussion on the web visit https://groups.google.com/d/msgid/beagleboard/1781cc2e-8871-4312-bd1e-a312ab32ed3en%40googlegroups.com.
