Just a moment ago, I was standing on cliffs edge, now I made a big step
forward .....
I'm able to generate a 10ns trigger pulse on __R30 Bit 4 :-)).
I placed the and instruction to clear Bit 4. Now it's clear, both indirect
loads ( lbbo &R ) are
responsible for the unexpected delay. I was expecting both are operating
from dram with
latency of 3 cycles. What is wrong? The data structure is expected in local
ram, to get best latency.
In C it's declared that way:
typedef struct Event Event_t;
struct Event
{
unsigned int time; // number of loops
unsigned char pattern; // Bit 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
// ------+---+---+---+----+---+----+---+
// | | | |~z34|z34|~z12|z12|
// ------+---+---+---+----+---+----+---+
};
int main( int argc, char *argv[])
{
int i;
int j;
unsigned char u;
*Event_t event_knoten[100];* // later on, r15 is pointing to that
address
...
...
...
ausgabe(pattern_liste.anzahl, &event_knoten[0].time, &handshake[0]) ;
***************** change to debug delay in assembler *******************
naechster:
*and r30, r30, 0xEF ; debug*
lbbo &r30, r15, 4, 1 ; (r15) = pattern <= slow
lbbo &r17, r15, 0, 2 ; load number of loops <= slow
Any hint how to make the lbbo &r.. faster?
I'm looking forward
Kasimir
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