Hello Walter
Two ansychronous processor's it's entirely possible eventually ones writing and 
other is reading and gets bad Data that's why they invented hardware dual port 
ram.
Ping pong circular buffer's work on one processor systems you disable 
interrupts in critical regions or lock it with a mutex controlled by RTOS.
Perhaps it's not critical
How long have you been waiting on an answer just curious?
Mark

Sent from Yahoo Mail on Android 
 
  On Fri, Jun 11, 2021 at 12:33 PM, Dennis Lee 
Bieber<dennis.l.bie...@gmail.com> wrote:   On Fri, 11 Jun 2021 09:44:27 -0700 
(PDT), in
gmane.comp.hardware.beagleboard.user Walter Cromer
<walterc-2dFtBuzUeF/tpnmuczy8bueocmrvl...@public.gmane.org> wrote:

>I can have PRU1 do all the ADC configuration including setting up steps 1, 
>2 and 3 to read three analog lines in one-shot mode while steps 4 & are set 
>up to read the other two analog lines in continous mode.  I'll write data 
>from steps 1, 2 and 3 into FIFO0 and 4 & 5 into FIFO1.  
>
>The question is can PRU0 read FIFO0 while PRU1 might try to read FIFO1 at 
>the same time?  

    Given that each PRU is capable of accessing the other's data RAM (as I
recall, each PRU sees its RAM at address 0, and sees the other's RAM at
some fixed offset), I'd probably use a few words of PRU0's RAM and have
PRU1 write into that space, along with a timestamp value -- PRU0 would look
for a change in the timestamp, then grab the ADC values (allowing PRU1 to
write new values while PRU0 processes the previous set -- Or PRU0 clears
the timestamp [which is no longer a timestamp] which PRU1 sees as "okay to
write new values", PRU1 then sets the timestamp byte to tell PRU0 "okay to
read". Closest I can come to a shared semaphore/mutex (are there any
synchronization primitives in the PRU runtime?).


-- 
Dennis L Bieber

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