On 15/06/2011 12:10, Paul Johnson wrote:
On Tue, Jun 14, 2011 at 11:56:04PM -0700, Beware wrote:
Hi
Sorry, i've been tired these past days.
So, this is what i want to do :
I've source code files in VHDL. I want to check that all specific keywords of
this language are in uppercase.
In fact, in my current script i read this file line per line and check others
rules.
Am i clear, now?
Here is some code that does this. I suggest you make sure you understand what
it does and check that it is correct. Call it by passing the names of your
VHDL files.
Note that this code isn't very clever. In particular you will get false
positives. To do the job properly you would need a VHDL parser. For that
reason I would suggest against modifying the code to alter the input file as
part of a checkin hook, for example.
(I prefer my keywords to be in lowercase.)
#!/usr/bin/perl
use strict;
use warnings;
my @keywords = qw
(
abs access after alias all and architecture array assert attribute begin
block body buffer bus case component configuration constant disconnect
downto else elsif end entity exit file for function generate generic group
guarded if impure in inertial inout is label library linkage literal loop
map mod nand new next nor not null of on open or others out package port
postponed procedure process pure range record register reject return rol
ror select severity signal shared sla sli sra srl subtype then to
transport type unaffected units until use variable wait when while with
xnor xor
);
my $kw = join "|", @keywords;
You would need
my $kw = join "|", map uc, @keywords;
:)
Rob
while (<>)
{
for my $w (/(\b$kw\b)/ig)
{
warn "Keyword '$w' not uppercase at $ARGV:$.\n" unless $w eq uc $w;
}
}
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