I just pushed this patch with slight change. As the baytrail-t has 4 EUs not
2, I chagne the max compute unit to 32 and max work group size to 256.
On Thu, Apr 10, 2014 at 04:25:12PM +0800, Chuanbo Weng wrote:
> Signed-off-by: Chuanbo Weng <chuanbo.w...@intel.com>
> ---
> src/cl_device_data.h | 8 +++++++-
> src/cl_device_id.c | 26 +++++++++++++++++++++++++-
> 2 files changed, 32 insertions(+), 2 deletions(-)
>
> diff --git a/src/cl_device_data.h b/src/cl_device_data.h
> index 9c18406..55327ec 100644
> --- a/src/cl_device_data.h
> +++ b/src/cl_device_data.h
> @@ -68,6 +68,8 @@
> #define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166
> #define PCI_CHIP_IVYBRIDGE_S_GT1 0x015a /* Server */
>
> +#define PCI_CHIP_BAYTRAIL_T 0x0F31
> +
> #define IS_IVB_GT1(devid) \
> (devid == PCI_CHIP_IVYBRIDGE_GT1 || \
> devid == PCI_CHIP_IVYBRIDGE_M_GT1 || \
> @@ -77,7 +79,10 @@
> (devid == PCI_CHIP_IVYBRIDGE_GT2 || \
> devid == PCI_CHIP_IVYBRIDGE_M_GT2)
>
> -#define IS_IVYBRIDGE(devid) (IS_IVB_GT1(devid) || IS_IVB_GT2(devid))
> +#define IS_BAYTRAIL_T(devid) \
> + (devid == PCI_CHIP_BAYTRAIL_T)
> +
> +#define IS_IVYBRIDGE(devid) (IS_IVB_GT1(devid) || IS_IVB_GT2(devid) ||
> IS_BAYTRAIL_T(devid))
> #define IS_GEN7(devid) IS_IVYBRIDGE(devid)
>
>
> @@ -121,6 +126,7 @@
> #define PCI_CHIP_HASWELL_CRW_M2 0x0D16 /* CRW GT2 mobile */
> #define PCI_CHIP_HASWELL_CRW_M3 0x0D26 /* CRW GT3 mobile */
>
> +
> #define IS_HASWELL(devid) ( \
> (devid) == PCI_CHIP_HASWELL_D1 || (devid) == PCI_CHIP_HASWELL_D2 || \
> (devid) == PCI_CHIP_HASWELL_D3 || (devid) == PCI_CHIP_HASWELL_S1 || \
> diff --git a/src/cl_device_id.c b/src/cl_device_id.c
> index 0426738..2a3124b 100644
> --- a/src/cl_device_id.c
> +++ b/src/cl_device_id.c
> @@ -57,6 +57,17 @@ static struct _cl_device_id intel_ivb_gt1_device = {
> #include "cl_gen7_device.h"
> };
>
> +static struct _cl_device_id intel_baytrail_t_device = {
> + INIT_ICD(dispatch)
> + .max_compute_unit = 16,
> + .max_thread_per_unit = 8,
> + .max_work_item_sizes = {512, 512, 512},
> + .max_work_group_size = 128,
> + .max_clock_frequency = 1000,
> + .wg_sz = 128,
> +#include "cl_gen7_device.h"
> +};
> +
> /* XXX we clone IVB for HSW now */
> static struct _cl_device_id intel_hsw_device = {
> INIT_ICD(dispatch)
> @@ -182,6 +193,14 @@ ivb_gt2_break:
> intel_ivb_gt2_device.platform = intel_platform;
> ret = &intel_ivb_gt2_device;
> break;
> +
> + case PCI_CHIP_BAYTRAIL_T:
> + DECL_INFO_STRING(baytrail_t_device_break, intel_baytrail_t_device,
> name, "Intel(R) HD Graphics Bay Trail-T");
> +baytrail_t_device_break:
> + intel_baytrail_t_device.vendor_id = device_id;
> + intel_baytrail_t_device.platform = intel_platform;
> + ret = &intel_baytrail_t_device;
> + break;
> default:
> printf("cl_get_gt_device(): error, unknown device\n");
> exit(1);
> @@ -252,6 +271,7 @@ cl_get_device_info(cl_device_id device,
> {
> if (UNLIKELY(device != &intel_ivb_gt1_device &&
> device != &intel_ivb_gt2_device &&
> + device != &intel_baytrail_t_device &&
> device != &intel_hsw_device))
> return CL_INVALID_DEVICE;
>
> @@ -338,11 +358,14 @@ cl_device_get_version(cl_device_id device, cl_int *ver)
> {
> if (UNLIKELY(device != &intel_ivb_gt1_device &&
> device != &intel_ivb_gt2_device &&
> + device != &intel_baytrail_t_device &&
> device != &intel_hsw_device))
> return CL_INVALID_DEVICE;
> if (ver == NULL)
> return CL_SUCCESS;
> - if (device == &intel_ivb_gt1_device || device == &intel_ivb_gt2_device)
> + if (device == &intel_ivb_gt1_device ||
> + device == &intel_ivb_gt2_device ||
> + device == &intel_baytrail_t_device)
> *ver = 7;
> else
> *ver = 75;
> @@ -374,6 +397,7 @@ cl_get_kernel_workgroup_info(cl_kernel kernel,
> {
> int err = CL_SUCCESS;
> if (UNLIKELY(device != &intel_ivb_gt1_device &&
> + device != &intel_baytrail_t_device &&
> device != &intel_ivb_gt2_device))
> return CL_INVALID_DEVICE;
>
> --
> 1.8.3.2
>
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