I will push this patch according to latest test result. Thanks.
On Tue, Jun 17, 2014 at 12:56:31PM +0800, Zhigang Gong wrote: > According to Yongjia's test report, it's better to keep > the same freqency of expiration with both simd8 and simd16 > mode. > > Signed-off-by: Zhigang Gong <zhigang.g...@intel.com> > --- > backend/src/backend/gen_reg_allocation.cpp | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/backend/src/backend/gen_reg_allocation.cpp > b/backend/src/backend/gen_reg_allocation.cpp > index d225bdb..02e0cde 100644 > --- a/backend/src/backend/gen_reg_allocation.cpp > +++ b/backend/src/backend/gen_reg_allocation.cpp > @@ -950,8 +950,7 @@ namespace gbe > // The tradeoff here is to reduce the freqency here. And if we are under > spilling > // then no need to reduce that freqency as the register pressure is the > most > // important factor. > - if (tick % (ctx.getSimdWidth() == 8 ? 12 : 4) == 0 > - || ctx.reservedSpillRegs != 0) > + if (tick % 12 == 0 || ctx.reservedSpillRegs != 0) > this->expireGRF(interval); > tick++; > // For some scalar byte register, it may be used as a destination > register > -- > 1.8.3.2 > > _______________________________________________ > Beignet mailing list > Beignet@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/beignet _______________________________________________ Beignet mailing list Beignet@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/beignet
