[Beignet] [PATCH 4/6] Correct indirect mode encoder setting for Gen7

[junyan . he]

From: Junyan He <junyan...@linux.intel.com>

Signed-off-by: Junyan He <junyan...@linux.intel.com>
---
 backend/src/backend/gen7_encoder.cpp |   14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/backend/src/backend/gen7_encoder.cpp 
b/backend/src/backend/gen7_encoder.cpp
index ecf5b39..a7d132c 100644
--- a/backend/src/backend/gen7_encoder.cpp
+++ b/backend/src/backend/gen7_encoder.cpp
@@ -118,14 +118,14 @@ namespace gbe
     } else {
       gen7_insn->bits1.ia1.src0_reg_file = GEN_GENERAL_REGISTER_FILE;
       gen7_insn->bits1.ia1.src0_reg_type = reg.type;
-      gen7_insn->bits2.ia1.src0_subreg_nr = 0;
-      gen7_insn->bits2.ia1.src0_indirect_offset = 0;
-      gen7_insn->bits2.ia1.src0_abs = 0;
-      gen7_insn->bits2.ia1.src0_negate = 0;
+      gen7_insn->bits2.ia1.src0_subreg_nr = reg.a0_subnr;
+      gen7_insn->bits2.ia1.src0_indirect_offset = reg.addr_imm;
+      gen7_insn->bits2.ia1.src0_abs = reg.absolute;
+      gen7_insn->bits2.ia1.src0_negate = reg.negation;
       gen7_insn->bits2.ia1.src0_address_mode = reg.address_mode;
-      gen7_insn->bits2.ia1.src0_horiz_stride = GEN_HORIZONTAL_STRIDE_0;
-      gen7_insn->bits2.ia1.src0_width = GEN_WIDTH_1;
-      gen7_insn->bits2.ia1.src0_vert_stride = 
GEN_VERTICAL_STRIDE_ONE_DIMENSIONAL;
+      gen7_insn->bits2.ia1.src0_horiz_stride = reg.hstride;
+      gen7_insn->bits2.ia1.src0_width = reg.width;
+      gen7_insn->bits2.ia1.src0_vert_stride = reg.vstride;
     }
   }
 
-- 
1.7.9.5

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