Hi Svein, I have reread about spec and find I may have some misunderstand about svm atomic, we have not fit the requirement for CL_MEM_SVM_ATOMIC now. The SVM are just support and as well as the 2.0 atomics. It seems that SVM atomic has some very strict requires to device and we haven’t implement that. Sorry for the wrong information.
Thanks Xiuli From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of Pan, Xiuli Sent: Monday, March 28, 2016 1:08 PM To: Svein Berge <sve...@pvv.org> Cc: beignet@lists.freedesktop.org Subject: Re: [Beignet] Low latency io Hi Svein, You will need some drm and intel linux kernel that later then 2016, Jan( I did not know the expect commit or date that they support what we need for SVM). And for llvm3.8 you only need a simple patch for pipe built-in to clang, you can download it from http://reviews.llvm.org/D15603. If you find anything wrong please feel free to ask, the OpenCL 2.0 is still under developed and we are welcomed you to have a try to see if there is any bug. Thanks Xiuli From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of Svein Berge Sent: Saturday, March 26, 2016 5:48 PM To: Pan, Xiuli <xiuli....@intel.com<mailto:xiuli....@intel.com>> Cc: beignet@lists.freedesktop.org<mailto:beignet@lists.freedesktop.org> Subject: Re: [Beignet] Low latency io Hello Xiuli, that’s great news! I tested the OCL20 branch in January. I don’t think it supported SVM atomics then, and I couldn’t get the OCL20 branch to build when I tried again last week. I will make a new attempt next week. You mention the need for an llvm patch to build it - could you tell me which patch that is? I have some question about the old style way, is the kernel need to be running all the time as the io changes the memory? And do some response to it at a low latency? That is correct. And could you explain the idea about how “invalidate a cache line from the kernel” can help with you requires? The idea is to write a loop in opencl which polls a memory location and flushes that memory location from cache so it will be read from system memory each time. But my understanding of the caching and coherence mechanisms involved is not good. Anyway, this point should be moot if you now support SVM atomics. Cheers, Svein
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