Joe Landman wrote: <snip> > That is an issue with this code. The Athlon has a 256k L2 last I > remember, and a 128k L1. Rather hard to keep lots of stuff in cache. Barton cores had 512k L2 as well as a faster front side bus.
> Right now the big issue we are running into for another aspect of this > project is the lack of a vector max/min function in SSE*. (If anyone > from AMD/Intel is listening, this is a *big* issue, and I even have a > rough idea how to do it "quickly" in SSE at the expense of many SSE > registers. > > Joe <snip> -- Geoffrey D. Jacobs MORE CORE AVAILABLE, BUT NONE FOR YOU. _______________________________________________ Beowulf mailing list, [email protected] To change your subscription (digest mode or unsubscribe) visit http://www.beowulf.org/mailman/listinfo/beowulf
