Bruno Coutinho wrote:
Yes, and more than an out of order processor. A out of order processor,
can reorder the instructions whenever a hazard occurs. A in order
processor, on the other hand, has to wait. With SMT, it can switch to
another thread.
And today memory access can stall up to hundreds of cycles, so any
processor can hide this latency by switching to another thread.
My gosh ... we have re-invented the Tera MTA. ...
But the you have to make sure the processor has enough cache and memory
bandwidth to handle the increased memory traffic (like Sun Niagara).
The problem with many (cores|threads) is that memory bandwidth wall. A
fixed size (B) pipe to memory, with N requesters on that pipe ...
--
Joseph Landman, Ph.D
Founder and CEO
Scalable Informatics LLC,
email: [EMAIL PROTECTED]
web : http://www.scalableinformatics.com
http://jackrabbit.scalableinformatics.com
phone: +1 734 786 8423
fax : +1 866 888 3112
cell : +1 734 612 4615
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