On Fri, Oct 25, 2013 at 11:54 AM, Jonathan S. Shapiro <[email protected]>wrote:
> Thanks for clarifying. I looked at the description, and it seems that they > have a fairly 1:1 encoding from IR instructions to bitcode instructions, > such that the majority of bitcode instructions translate 1:1 into target > instructions on RISC machines. That would make it a DBT scheme in my mind. > Bitcode is just a binary representation of LLVM IR. A translator from LLVM to machine code still needs to do register allocation, which makes it not-DBT by your earlier classification, right? > For x86 instructions they have to do more work, or they could choose to > eat emitting multiple target instructions for each bitcode instruction. > > Working at the binary instruction level like this doesn't preclude doing > sophisticated dynamic translation. What it does is enable a fast-and-light > translation mode. When the instruction set is at this level, you can > translate a bitcode instruction to a target instruction in 12-20 cycles per > instruction (which is *very* low), and sometimes faster. That's low > enough that trace linearization erases the costs of translation. > > Come to that, this format is easier to decode than x86, so it's probably > easier to translate than what HDTrans needed for pentium->pentium > translation. > > > > On Fri, Oct 25, 2013 at 8:14 AM, Ben Kloosterman <[email protected]>wrote: > >> >> Bit code . IR files become .bc files which are processed by the execution >> engine.. >> http://llvm.org/docs/BitCodeFormat.html >> >> It can also run almost fully compiled assemblies which is probably a >> DBT engine but i havent followed that through . >> >> Ben >> >> _______________________________________________ >> bitc-dev mailing list >> [email protected] >> http://www.coyotos.org/mailman/listinfo/bitc-dev >> >> > > _______________________________________________ > bitc-dev mailing list > [email protected] > http://www.coyotos.org/mailman/listinfo/bitc-dev > >
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