On Wed, Oct 21, 2020 at 11:20:17AM +0100, Grant Likely wrote:
> > +   HS Mode
> > +      Hypervisor-extended-supervisor mode which virtualizes the supervisor 
> > mode.
> > +
> > +   U Mode
> > +      User mode where userspace application is expected to run.
> > +
> > +   HSM
> > +      Hart State Management (HSM) is an SBI extension that enables the 
> > supervisor
> > +      mode software to implement ordered booting.
> > +
> > +   SEE
> > +      Supervisor Execution Environment in RISC-V. This can be M mode or HS 
> > mode.
> > +
> > +   SBI
> > +      Supervisor Binary Interface. This is an interface between SEE and 
> > supervisor
> > +      mode in RISC-V.
> > +
> > +   RV32
> > +      32 bit execution mode in RISC-V.
> > +
> > +   RV64
> > +      64 bit execution mode in RISC-V. > +
> 
> I disagree with Daniel. I think all the RISC-V specific terms should be
> collected into a sub header, and the same should be done for ARM and
> AArch64. Mixing architecture specific terms together seems confusing to me.

No worries. It was a weak preference on my side! I can live with
headings...


Daniel.
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