https://sourceware.org/bugzilla/show_bug.cgi?id=28733
Bug ID: 28733 Summary: RISC-V: Bad errors on fence.i and CSR ISA checking Product: binutils Version: unspecified Status: NEW Severity: normal Priority: P2 Component: gas Assignee: unassigned at sourceware dot org Reporter: nelsonc1225 at sourceware dot org Target Milestone: --- For now we just report the errors "unrecognized opcode" for the instruction which needs to enable some specific extensions. For example, nelson@LAPTOP-QFSGI1F2:~/test$ cat tmp.s fence.i csrr a0, fcsr csrr a0, seed sh1add a0, a1, a2 nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf64-upstream/build-install/bin/riscv64-unknown-elf-as -march=rv32i2p1 tmp.s -o tmp.o tmp.s: Assembler messages: tmp.s:1: Error: unrecognized opcode `fence.i' tmp.s:2: Error: unrecognized opcode `csrr a0,fcsr' tmp.s:3: Error: unrecognized opcode `csrr a0,seed' tmp.s:4: Error: unrecognized opcode `sh1add a0,a1,a2' nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf64-upstream/build-install/bin/riscv64-unknown-elf-as -march=rv32i2p1_zicsr_zifencei_zba tmp.s -o tmp.o It would great if we can show the more details like "unrecognized opcode `fence.i', need to enable zifencei extension...". Besides, if we enable the -mcsr-check, then, nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf64-upstream/build-install/bin/riscv64-unknown-elf-as -march=rv32i2p1_zicsr_zifencei_zba -mcsr-check tmp.s -o tmp.o tmp.s: Assembler messages: tmp.s:2: Warning: invalid CSR `fcsr' for the current ISA tmp.s:3: Warning: invalid CSR `seed' for the current ISA This is also the similar works, we can report something like "fcsr needs f extension" and "seed needs zkr extension". The more TODO, we can also try to improve the whole error reports in the riscv_ip, since for now we just report "illegal operand", and sometimes it is really not friendly to users. -- You are receiving this mail because: You are on the CC list for the bug.