https://sourceware.org/bugzilla/show_bug.cgi?id=32704
Bug ID: 32704
Summary: Improve __gcc_isr prologue generation
Product: binutils
Version: 2.44
Status: NEW
Severity: enhancement
Priority: P3
Component: gas
Assignee: unassigned at sourceware dot org
Reporter: gjl at gcc dot gnu.org
Target Milestone: ---
Target: avr
In code like
volatile char var;
__attribute((signal))
void __vector1 ()
{
var = 1;
var = 0;
}
the body of the ISR needs zero_reg, doesn't clobber SREG and uses a reg >= R16:
__vector1:
__gcc_isr 1
ldi r24, 1
sts var, r24
sts var, __zero_reg__
__gcc_isr 2
reti
__gcc_isr 0,r24
In that situation, the prologue from __gcc_isr can be improved from the current
000000f2 <__vector1>:
f2: 1f 92 push r1
f4: 1f b6 in r1, 0x3f ; 63
f6: 1f 92 push r1
f8: 11 24 eor r1, r1
fa: 8f 93 push r24
that clobbers SREG just for the purpose of CLR R1, to something like
push r1
push r24
ldi r24, 0
mov r1, r24
which is shorted, faster and uses less stack space.
--
You are receiving this mail because:
You are on the CC list for the bug.
