https://sourceware.org/bugzilla/show_bug.cgi?id=32791
Bug ID: 32791
Summary: (RISC-V) Possible misassembly of three-register
cm.push
Product: binutils
Version: 2.44
Status: UNCONFIRMED
Severity: normal
Priority: P2
Component: gas
Assignee: unassigned at sourceware dot org
Reporter: wren6991 at gmail dot com
Target Milestone: ---
$ cat repro.S
cm.push {ra, s0, s1}, -16
$ /opt/riscv/gcc14/bin/riscv32-unknown-elf-as -march=rv32i_zca_zcmp -c repro.S
$ /opt/riscv/gcc14/bin/riscv32-unknown-elf-objdump -d a.out
a.out: file format elf32-littleriscv
Disassembly of section .text:
00000000 <.text>:
0: b852 cm.push {ra,s0},-16
When I write a push with register list {ra, s0, s1}, I expect either:
* a 3-register cm.push opcode (b862)
* a syntax error
It actually generates a 2-register opcode (b852) which silently changes the
behaviour of my program.
I do get the correct opcode if I write cm.push {ra, s0-s1} but I have a lot of
muscle memory for Cortex-M GAS where push {r0-r2} is an equivalent shorthand
for push {r0, r1, r2} for example.
The binutils version is:
$ /opt/riscv/gcc14/bin/riscv32-unknown-elf-as --version
GNU assembler (GNU Binutils) 2.44.50.20250308
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