hello ,
------------cut-x-here---------
$uname -p
unknown
$uname -m
x86_64
$uname -a
Linux debian 3.11-1-amd64 #1 SMP Debian 3.11.5-1 (2013-10-17) x86_64 GNU/Linux
$
---------cut-x-here----------
i will attach the output of cpuid command.
http://www.ka9q.net/code/cpuid/
I think it is not a bug to show "unknown" for -p
my processor is AMD A-Series
is possible to make "unknown" to the correct processor type.
Thanks.
/Jeffrin.
CPU 0:
vendor_id = "AuthenticAMD"
version information (1/eax):
processor type = primary processor (0)
family = Intel Pentium 4/Pentium D/Pentium Extreme
Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon
XP-M/Opteron/Sempron/Turion (15)
model = 0x3 (3)
stepping id = 0x1 (1)
extended family = 0x6 (6)
extended model = 0x1 (1)
(simple synth) = AMD A-Series / AMD R-Series / Athlon Dual-Core / Athlon
Quad-Core / Sempron Dual-Core / FirePro (Richland RL-A1), 32nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x0 (0)
cpu count = 0x2 (2)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
virtual-8086 mode enhancement = true
debugging extensions = true
page size extensions = true
time stamp counter = true
RDMSR and WRMSR support = true
physical address extensions = true
machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
memory type range registers = true
PTE global bit = true
machine check architecture = true
conditional move/compare instruction = true
page attribute table = true
page size extension = true
processor serial number = false
CLFLUSH instruction = true
debug store = false
thermal monitor and clock ctrl = false
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
self snoop = false
hyper-threading / multi-core supported = true
therm. monitor = false
IA64 = false
pending break event = false
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
64-bit debug store = false
MONITOR/MWAIT = true
CPL-qualified debug store = false
VMX: virtual machine extensions = false
SMX: safer mode extensions = false
Enhanced Intel SpeedStep Technology = false
thermal monitor 2 = false
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
FMA instruction = true
CMPXCHG16B instruction = true
xTPR disable = false
perfmon and debug = false
process context identifiers = false
direct cache access = false
SSE4.1 extensions = true
SSE4.2 extensions = true
extended xAPIC support = false
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = false
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = false
hypervisor guest status = false
cache and TLB information (2):
processor serial number: 0061-0F31-0000-0000-0000-0000
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x0 (0)
number of C2 sub C-states using MWAIT = 0x0 (0)
number of C3/C6 sub C-states using MWAIT = 0x0 (0)
number of C4/C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = false
Intel Turbo Boost Technology = false
ARAT always running APIC timer = false
PLN power limit notification = false
ECMD extended clock modulation duty = false
PTM package thermal management = false
digital thermometer thresholds = 0x0 (0)
ACNT/MCNT supported performance measure = true
ACNT2 available = false
performance-energy bias capability = false
extended feature flags (7):
FSGSBASE instructions = false
BMI instruction = true
SMEP support = false
enhanced REP MOVSB/STOSB = false
INVPCID instruction = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 0
Architecture Performance Monitoring Features (0xa/eax):
version ID = 0x0 (0)
number of counters per logical processor = 0x0 (0)
bit width of counter = 0x0 (0)
length of EBX bit vector = 0x0 (0)
Architecture Performance Monitoring Features (0xa/ebx):
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
Architecture Performance Monitoring Features (0xa/edx):
number of fixed counters = 0x0 (0)
bit width of fixed counters = 0x0 (0)
0x0000000c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x000003c0 (960)
XCR0 upper 32 bits valid bit field mask = 0x40000000
YMM features (0xd/2):
YMM save state byte size = 0x00000100 (256)
YMM save state byte offset = 0x00000240 (576)
LWP features (0xd/0x3e):
LWP save state byte size = 0x00000080 (128)
LWP save state byte offset = 0x00000340 (832)
extended processor signature (0x80000001/eax):
family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
model = 0x3 (3)
stepping id = 0x1 (1)
extended family = 0x6 (6)
extended model = 0x1 (1)
(simple synth) = AMD A-Series / AMD R-Series / Athlon Dual-Core / Athlon
Quad-Core / Sempron Dual-Core / FirePro (Richland RL-A1), 32nm
extended feature flags (0x80000001/edx):
x87 FPU on chip = true
virtual-8086 mode enhancement = true
debugging extensions = true
page size extensions = true
time stamp counter = true
RDMSR and WRMSR support = true
physical address extensions = true
machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSCALL and SYSRET instructions = true
memory type range registers = true
global paging extension = true
machine check architecture = true
conditional move/compare instruction = true
page attribute table = true
page size extension = true
multiprocessing capable = false
no-execute page protection = true
AMD multimedia instruction extensions = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
1-GB large page support = true
RDTSCP = true
long mode (AA-64) = true
3DNow! instruction extensions = false
3DNow! instructions = false
extended brand id (0x80000001/ebx):
raw = 0x20000000 (536870912)
BrandId = 0x0 (0)
AMD feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
CMP Legacy = true
SVM: secure virtual machine = true
extended APIC space = true
AltMovCr8 = true
LZCNT advanced bit manipulation = true
SSE4A support = true
misaligned SSE mode = true
PREFETCH/PREFETCHW instructions = true
OS visible workaround = true
instruction based sampling = true
XOP support = true
SKINIT/STGI support = true
watchdog timer support = true
lightweight profiling support = true
4-operand FMA instruction = true
NodeId MSR C001100C = true
TBM support = true
topology extensions = true
brand = "AMD A4-4000 APU with Radeon(tm) HD Graphics "
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x18 (24)
instruction associativity = 0xff (255)
data # entries = 0x40 (64)
data associativity = 0xff (255)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x30 (48)
instruction associativity = 0xff (255)
data # entries = 0x40 (64)
data associativity = 0xff (255)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x1 (1)
associativity = 0x4 (4)
size (Kb) = 0x10 (16)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x40 (64)
lines per tag = 0x1 (1)
associativity = 0x2 (2)
size (Kb) = 0x40 (64)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x400 (1024)
instruction associativity = 8-way (6)
data # entries = 0x400 (1024)
data associativity = 8-way (6)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x200 (512)
instruction associativity = 4-way (4)
data # entries = 0x400 (1024)
data associativity = 8-way (6)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x1 (1)
associativity = 16-way (8)
size (Kb) = 0x400 (1024)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512Kb units) = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
temperature sensing diode = true
frequency ID (FID) control = false
voltage ID (VID) control = false
thermal trip (TTP) = true
thermal monitor (TM) = true
software thermal control (STC) = false
100 MHz multiplier control = true
hardware P-State control = true
TscInvariant = true
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x30 (48)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Logical CPU cores (0x80000008/ecx):
number of CPU cores - 1 = 0x1 (1)
ApicIdCoreIdSize = 0x4 (4)
SVM Secure Virtual Machine (0x8000000a/eax):
SvmRev: SVM revision = 0x1 (1)
SVM Secure Virtual Machine (0x8000000a/edx):
nested paging = true
LBR virtualization = true
SVM lock = true
NRIP save = true
MSR based TSC rate control = true
VMCB clean bits support = true
flush by ASID = true
decode assists = true
SSSE3/SSE5 opcode set disable = false
pause intercept filter = true
pause filter threshold = true
NASID: number of address space identifiers = 0x10000 (65536):
L1 TLB information: 1G pages (0x80000019/eax):
instruction # entries = 0x18 (24)
instruction associativity = full (15)
data # entries = 0x40 (64)
data associativity = full (15)
L2 TLB information: 1G pages (0x80000019/ebx):
instruction # entries = 0x400 (1024)
instruction associativity = 8-way (6)
data # entries = 0x400 (1024)
data associativity = 8-way (6)
SVM Secure Virtual Machine (0x8000001a/eax):
128-bit SSE executed full-width = true
MOVU* better than MOVL*/MOVH* = true
Instruction Based Sampling Identifiers (0x8000001b/eax):
IBS feature flags valid = true
IBS fetch sampling = true
IBS execution sampling = true
read write of op counter = true
op counting mode = true
branch target address reporting = true
IbsOpCurCnt and IbsOpMaxCnt extend 7 = true
invalid RIP indication supported = true
Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
lightweight profiling = false
LWPVAL instruction = false
instruction retired event = false
branch retired event = false
DC miss event = false
core clocks not halted event = false
core reference clocks not halted event = false
interrupt on threshold overflow = false
Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
lightweight profiling = true
LWPVAL instruction = true
instruction retired event = true
branch retired event = true
DC miss event = false
core clocks not halted event = false
core reference clocks not halted event = false
interrupt on threshold overflow = true
Lightweight Profiling Capabilities (0x8000001c/ebx):
LWPCB byte size = 0x13 (19)
event record byte size = 0x20 (32)
maximum EventId = 0x3 (3)
EventInterval1 field offset = 0x80 (128)
Lightweight Profiling Capabilities (0x8000001c/ecx):
latency counter bit size = 0x0 (0)
data cache miss address valid = false
amount cache latency is rounded = 0x0 (0)
LWP implementation version = 0x1 (1)
event ring buffer size in records = 0x1 (1)
branch prediction filtering = false
IP filtering = false
cache level filtering = false
cache latency filteing = false
--- cache 0 ---
type = data (1)
level = 0x1 (1)
self-initializing = true
fully associative = false
extra cores sharing this cache = 0x0 (0)
line size in bytes = 0x3f (63)
physical line partitions = 0x0 (0)
number of ways = 0x3 (3)
number of sets = 63
write-back invalidate = false
cache inclusive of lower levels = false
extended APIC ID = 16
Extended APIC ID (0x8000001e/ebx):
compute unit ID = 0x0 (0)
cores per compute unit - 1 = 0x1 (1)
Extended APIC ID (0x8000001e/ecx):
node ID = 0x0 (0)
nodes per processor = 1 node (0)
(multi-processing synth): multi-core (c=2)
(multi-processing method): AMD
(APIC widths synth): CORE_width=1 SMT_width=0
(APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=0
(synth) = AMD A-Series / AMD R-Series / Athlon Dual-Core / Athlon Quad-Core
/ Sempron Dual-Core / FirePro (Richland RL-A1), 32nm
CPU 1:
vendor_id = "AuthenticAMD"
version information (1/eax):
processor type = primary processor (0)
family = Intel Pentium 4/Pentium D/Pentium Extreme
Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon
XP-M/Opteron/Sempron/Turion (15)
model = 0x3 (3)
stepping id = 0x1 (1)
extended family = 0x6 (6)
extended model = 0x1 (1)
(simple synth) = AMD A-Series / AMD R-Series / Athlon Dual-Core / Athlon
Quad-Core / Sempron Dual-Core / FirePro (Richland RL-A1), 32nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x1 (1)
cpu count = 0x2 (2)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
virtual-8086 mode enhancement = true
debugging extensions = true
page size extensions = true
time stamp counter = true
RDMSR and WRMSR support = true
physical address extensions = true
machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
memory type range registers = true
PTE global bit = true
machine check architecture = true
conditional move/compare instruction = true
page attribute table = true
page size extension = true
processor serial number = false
CLFLUSH instruction = true
debug store = false
thermal monitor and clock ctrl = false
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
self snoop = false
hyper-threading / multi-core supported = true
therm. monitor = false
IA64 = false
pending break event = false
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
64-bit debug store = false
MONITOR/MWAIT = true
CPL-qualified debug store = false
VMX: virtual machine extensions = false
SMX: safer mode extensions = false
Enhanced Intel SpeedStep Technology = false
thermal monitor 2 = false
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
FMA instruction = true
CMPXCHG16B instruction = true
xTPR disable = false
perfmon and debug = false
process context identifiers = false
direct cache access = false
SSE4.1 extensions = true
SSE4.2 extensions = true
extended xAPIC support = false
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = false
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = false
hypervisor guest status = false
cache and TLB information (2):
processor serial number: 0061-0F31-0000-0000-0000-0000
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x0 (0)
number of C2 sub C-states using MWAIT = 0x0 (0)
number of C3/C6 sub C-states using MWAIT = 0x0 (0)
number of C4/C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = false
Intel Turbo Boost Technology = false
ARAT always running APIC timer = false
PLN power limit notification = false
ECMD extended clock modulation duty = false
PTM package thermal management = false
digital thermometer thresholds = 0x0 (0)
ACNT/MCNT supported performance measure = true
ACNT2 available = false
performance-energy bias capability = false
extended feature flags (7):
FSGSBASE instructions = false
BMI instruction = true
SMEP support = false
enhanced REP MOVSB/STOSB = false
INVPCID instruction = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 0
Architecture Performance Monitoring Features (0xa/eax):
version ID = 0x0 (0)
number of counters per logical processor = 0x0 (0)
bit width of counter = 0x0 (0)
length of EBX bit vector = 0x0 (0)
Architecture Performance Monitoring Features (0xa/ebx):
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
Architecture Performance Monitoring Features (0xa/edx):
number of fixed counters = 0x0 (0)
bit width of fixed counters = 0x0 (0)
0x0000000c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x000003c0 (960)
XCR0 upper 32 bits valid bit field mask = 0x40000000
YMM features (0xd/2):
YMM save state byte size = 0x00000100 (256)
YMM save state byte offset = 0x00000240 (576)
LWP features (0xd/0x3e):
LWP save state byte size = 0x00000080 (128)
LWP save state byte offset = 0x00000340 (832)
extended processor signature (0x80000001/eax):
family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
model = 0x3 (3)
stepping id = 0x1 (1)
extended family = 0x6 (6)
extended model = 0x1 (1)
(simple synth) = AMD A-Series / AMD R-Series / Athlon Dual-Core / Athlon
Quad-Core / Sempron Dual-Core / FirePro (Richland RL-A1), 32nm
extended feature flags (0x80000001/edx):
x87 FPU on chip = true
virtual-8086 mode enhancement = true
debugging extensions = true
page size extensions = true
time stamp counter = true
RDMSR and WRMSR support = true
physical address extensions = true
machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSCALL and SYSRET instructions = true
memory type range registers = true
global paging extension = true
machine check architecture = true
conditional move/compare instruction = true
page attribute table = true
page size extension = true
multiprocessing capable = false
no-execute page protection = true
AMD multimedia instruction extensions = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
1-GB large page support = true
RDTSCP = true
long mode (AA-64) = true
3DNow! instruction extensions = false
3DNow! instructions = false
extended brand id (0x80000001/ebx):
raw = 0x20000000 (536870912)
BrandId = 0x0 (0)
AMD feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
CMP Legacy = true
SVM: secure virtual machine = true
extended APIC space = true
AltMovCr8 = true
LZCNT advanced bit manipulation = true
SSE4A support = true
misaligned SSE mode = true
PREFETCH/PREFETCHW instructions = true
OS visible workaround = true
instruction based sampling = true
XOP support = true
SKINIT/STGI support = true
watchdog timer support = true
lightweight profiling support = true
4-operand FMA instruction = true
NodeId MSR C001100C = true
TBM support = true
topology extensions = true
brand = "AMD A4-4000 APU with Radeon(tm) HD Graphics "
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x18 (24)
instruction associativity = 0xff (255)
data # entries = 0x40 (64)
data associativity = 0xff (255)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x30 (48)
instruction associativity = 0xff (255)
data # entries = 0x40 (64)
data associativity = 0xff (255)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x1 (1)
associativity = 0x4 (4)
size (Kb) = 0x10 (16)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x40 (64)
lines per tag = 0x1 (1)
associativity = 0x2 (2)
size (Kb) = 0x40 (64)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x400 (1024)
instruction associativity = 8-way (6)
data # entries = 0x400 (1024)
data associativity = 8-way (6)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x200 (512)
instruction associativity = 4-way (4)
data # entries = 0x400 (1024)
data associativity = 8-way (6)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x1 (1)
associativity = 16-way (8)
size (Kb) = 0x400 (1024)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512Kb units) = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
temperature sensing diode = true
frequency ID (FID) control = false
voltage ID (VID) control = false
thermal trip (TTP) = true
thermal monitor (TM) = true
software thermal control (STC) = false
100 MHz multiplier control = true
hardware P-State control = true
TscInvariant = true
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x30 (48)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Logical CPU cores (0x80000008/ecx):
number of CPU cores - 1 = 0x1 (1)
ApicIdCoreIdSize = 0x4 (4)
SVM Secure Virtual Machine (0x8000000a/eax):
SvmRev: SVM revision = 0x1 (1)
SVM Secure Virtual Machine (0x8000000a/edx):
nested paging = true
LBR virtualization = true
SVM lock = true
NRIP save = true
MSR based TSC rate control = true
VMCB clean bits support = true
flush by ASID = true
decode assists = true
SSSE3/SSE5 opcode set disable = false
pause intercept filter = true
pause filter threshold = true
NASID: number of address space identifiers = 0x10000 (65536):
L1 TLB information: 1G pages (0x80000019/eax):
instruction # entries = 0x18 (24)
instruction associativity = full (15)
data # entries = 0x40 (64)
data associativity = full (15)
L2 TLB information: 1G pages (0x80000019/ebx):
instruction # entries = 0x400 (1024)
instruction associativity = 8-way (6)
data # entries = 0x400 (1024)
data associativity = 8-way (6)
SVM Secure Virtual Machine (0x8000001a/eax):
128-bit SSE executed full-width = true
MOVU* better than MOVL*/MOVH* = true
Instruction Based Sampling Identifiers (0x8000001b/eax):
IBS feature flags valid = true
IBS fetch sampling = true
IBS execution sampling = true
read write of op counter = true
op counting mode = true
branch target address reporting = true
IbsOpCurCnt and IbsOpMaxCnt extend 7 = true
invalid RIP indication supported = true
Lightweight Profiling Capabilities: Availability (0x8000001c/eax):
lightweight profiling = false
LWPVAL instruction = false
instruction retired event = false
branch retired event = false
DC miss event = false
core clocks not halted event = false
core reference clocks not halted event = false
interrupt on threshold overflow = false
Lightweight Profiling Capabilities: Supported (0x8000001c/edx):
lightweight profiling = true
LWPVAL instruction = true
instruction retired event = true
branch retired event = true
DC miss event = false
core clocks not halted event = false
core reference clocks not halted event = false
interrupt on threshold overflow = true
Lightweight Profiling Capabilities (0x8000001c/ebx):
LWPCB byte size = 0x13 (19)
event record byte size = 0x20 (32)
maximum EventId = 0x3 (3)
EventInterval1 field offset = 0x80 (128)
Lightweight Profiling Capabilities (0x8000001c/ecx):
latency counter bit size = 0x0 (0)
data cache miss address valid = false
amount cache latency is rounded = 0x0 (0)
LWP implementation version = 0x1 (1)
event ring buffer size in records = 0x1 (1)
branch prediction filtering = false
IP filtering = false
cache level filtering = false
cache latency filteing = false
--- cache 0 ---
type = data (1)
level = 0x1 (1)
self-initializing = true
fully associative = false
extra cores sharing this cache = 0x0 (0)
line size in bytes = 0x3f (63)
physical line partitions = 0x0 (0)
number of ways = 0x3 (3)
number of sets = 63
write-back invalidate = false
cache inclusive of lower levels = false
extended APIC ID = 17
Extended APIC ID (0x8000001e/ebx):
compute unit ID = 0x0 (0)
cores per compute unit - 1 = 0x1 (1)
Extended APIC ID (0x8000001e/ecx):
node ID = 0x0 (0)
nodes per processor = 1 node (0)
(multi-processing synth): multi-core (c=2)
(multi-processing method): AMD
(APIC widths synth): CORE_width=1 SMT_width=0
(APIC synth): PKG_ID=0 CORE_ID=1 SMT_ID=0
(synth) = AMD A-Series / AMD R-Series / Athlon Dual-Core / Athlon Quad-Core
/ Sempron Dual-Core / FirePro (Richland RL-A1), 32nm
