Hi Dima,
Thanks for the tip on connecting via the P-Active arc, that seems to work.
I'll have to experiment a bit more to see if I can get rid of other errors of
this type. There are a lot of overlap and touching errors in the padframe I
downloaded from Mosis but I don't think there's anything I can do about that
(beyond re-laying out the pads).
Thank very much!
Pierce
[EMAIL PROTECTED] wrote:
Hello Pierce,
Try to connect port of P-transistor and Metal1-P
Active contact by
a short P-Active arc.
If nodes are not connected by arc, Electric doesn't
know that you want them to be connected,
and it thinks that you overlapped them accidently.
-Dima
Hello,
Is there a way to stop designated DRC errors? For example, when a Metal1-P
Active connector is placed on a P transistor active region, a DRC error is
generated:
DRC error 4 of 7: Spacing (layer P-Active): node Metal-1-P-Active-Con
OVERLAPS arc P-Active [rule 2.2]
However I am merely connecting the transistor drain, so I would like to
suppress this error.
Other times like layers might be intended to touch and a DRC error is
correctly generated. However, I would often like to selectively suppress these
errors as well. Is there a way to do this?
Thanks very much,
Pierce
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