Dear Steven,
as mentioned before I highly appreciate that someone is spending
his precious time to code such things.
I will send a small example immediately.
Just one simple question in advance:
I'm preprocessing my standard vcd files to make your tool
capable of reading it.
Do you accept any signal definition in addition to
$var wire 1 #! my_signal $end
?
Verilog & Modelsim use the statement input and output and the vcd
spec mentiones
much more like supply0 / supply 1.
How can I distinguish the value "z" from the value "x" in the
graphical display ?
"1" is a top line, "0" is a bottom line, "x" and "z" are both a
rectangular filled box. (all signals are red).
Best regards & thanks a lot
Ralf
P.S.
Please feel free to raise any question related to VCD or VCDE to me, as
I'm used to work with these
files every day ;-)
Steven Rubin schrieb:
I highly appreciate that you have coded this nice tool,
as it allows me to show customers some diagrams without
requesting them to dive through endless listings.
I could manage to convert a standard vcd file from verilog or modelsim
to be read into electric, but I could not manage to view the states Z
or z
and maybe resistive 1 or resistive 0.
Just a sample dump file holding the slang used to do this would be fine.
The Electric VCD reader for Verilog output handles just 4 states: 0,
1, X, and Z. It does not handle "resistive 1" or "resistive 0". I am
unfamiliar with VCD file syntax for those states. If you have a SMALL
example file, please send it to me.
-Steven Rubin
--
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
NEC Electronics (Europe) GmbH
Ralf Derscheid
Expert Assistant Manager
Marketing Asic Solutions
Industrial & Distribution Business Unit
Arcadiastrasse 10 Tel. +49-211-6503-1380
D-40472 Duesseldorf Fax. +49-211-6503-6380
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> ;-)
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