On Wed, Dec 08, 2010 at 02:52:10AM -0300, Diego Nieto Cid wrote: > Writting CSR0_NORMAL to pcnet's CSR0 register sets the 'interruption enabled' > bit allowing the hardware to raise interruptions. > > So, why would such an amount of interruptions be triggered? > Their alternating pattern is also interesting. What's interrupt 7 and > how is it related to 11?
That's some nice debugging work. But I don't understand why you're asking the question. You have a patched qemu, you seem to know how to deal with gdb, is there something preventing you from inspecting the kernel (and more specifically, the IDT) to determine what interrupts 7 and 11 are ? -- Richard Braun
