Hello,

Thanks for your proposal, but I don't understand what this is.

What is the purpose? How does it integrate in the existing
infrastructure?

Note that we usually plan to *not* write drivers ourselves, but rather
rely on the rump-provided drivers, so we do not have to handle the
maintenance of the drivers.

With regards,
Samuel

Ahemd Khider, le jeu. 13 août 2026 03:41:31 +0300, a ecrit:
> From: astra <[email protected]>
> 
> ---
>  libsound/audio.c  |  64 ++++++++++++++++++++++++++
>  libsound/audio.h  | 111 ++++++++++++++++++++++++++++++++++++++++++++++
>  libsound/makefile |   7 +++
>  3 files changed, 182 insertions(+)
>  create mode 100644 libsound/audio.c
>  create mode 100644 libsound/audio.h
>  create mode 100644 libsound/makefile
> 
> diff --git a/libsound/audio.c b/libsound/audio.c
> new file mode 100644
> index 00000000..7d18e41f
> --- /dev/null
> +++ b/libsound/audio.c
> @@ -0,0 +1,64 @@
> +/* This File Is Part Of Hurd Audio Interface System (Haudis) */
> +/* This file Is Under GNU General Public License Version 3 (GPL3) */ 
> +/* Original Author : AHMED KHIDER (2026) */
> +
> +
> +
> +#include "audio.h"
> +
> +bool init_hda_enge(volatile uint32_t *cntlr)
> +{
> +
> +
> +  /* Controller Initialization */
> +
> +  cntlr[HDA_GC] &= ~RESET;
> +  uint8_t wait = 50;
> +
> +  while ( (wait--) > 0)
> +  { /* Wait Until Read Back */ }
> +
> +  if (wait <= 0) return 1;
> +
> +  cntlr[HDA_GC] |= RESET;
> +
> +  while ( (wait--) > 0)
> +  { /* Wait Until Read Back */ }
> +
> +  if (wait <= 0) return 1;
> +  
> +  if ((cntlr[HDA_ST] & 0x0F) != 0) return 1;
> +  
> +  /* CORB Initialization */
> +  
> +  cntlr[HDA_CORB_CNTRL] = 0x00;
> +  while (cntlr[HDA_CORB_CNTRL] & 2);
> +  
> +  cntlr[HDA_CORB_LBA] &= 0xFFFFFFFF;
> +  cntlr[HDA_CORB_UBA] = (*cntlr >> 16) & 0xFFFFFFFF;
> +
> +  cntlr[HDA_CORB_WP] = 0x0000;
> +
> +  cntlr[HDA_CORB_RP] &= (1 << 15); /* 0x8000 */
> +  while( cntlr[HDA_CORB_RP] &= (1 << 15) );
> +  cntlr[HDA_CORB_RP] = 0x0000;
> +  cntlr[HDA_CORB_CNTRL] = 0x02;
> +
> +
> +  /* RIRB Initialization */
> +
> +  cntlr[HDA_RIRB_CNTRL]=0x00;
> +  while (cntlr[HDA_RIRB_CNTRL] & 2);
> +  
> +  cntlr[HDA_RIRB_LBA] &= 0xFFFFFFFFF;
> +  cntlr[HDA_RIRB_UBA] = (*cntlr >> 16) & 0xFFFFFFFF;
> +  
> +  cntlr[HDA_RIRB_SIZE] = 0x02;
> +
> +  cntlr[HDA_CORB_WP] = (1 << 15);
> +  while( cntlr[HDA_RIRB_WP] &= (1 << 15) ); /* 0x8000 */ 
> +  cntlr[HDA_RIRB_WP] = 0x0000;
> +  cntlr[HDA_RIRB_CNTRL] = 0x02;
> +  
> +  return 0; 
> +}
> diff --git a/libsound/audio.h b/libsound/audio.h
> new file mode 100644
> index 00000000..2b07c902
> --- /dev/null
> +++ b/libsound/audio.h
> @@ -0,0 +1,111 @@
> +/* This File Is Part Of Hurd Audio Interface System (Haudis) */
> +/* This file Is Under GNU General Public License Version 3 (GPL3) */ 
> +/* Original Author : AHMED KHIDER (2026) */ 
> +
> +#ifndef    HURD_AUDIO_INTERFACE
> +#define    HURD_AUDIO_INTERFACE
> +
> +#include <stdint.h>
> +#include <stdbool.h>
> +
> +/* Intel High Definition Audio */
> +
> +#ifndef  INTEL_HDA_REG
> +#define  INTEL_HDA_REG 
> +#define HDA_GCP           0x00  /* Global Capablities */
> +#define HDA_MNV           0x02  /* Minor Version */
> +#define HDA_MJV           0x03  /* Major Version */
> +#define HDA_GC            0x08  /* Global control */
> +#define HDA_ST            0x0E  /* Status Test */  
> +#define HDA_IC            0x20  /* Interrupt Control */
> +#define HDA_STREAM_SYNCH  0x34  /* Stream Synchronization */
> +#define HDA_CORB_LBA      0x40  /* CORB Lower Base Address */
> +#define HDA_CORB_UBA      0x44  /* CORB Upper Base Address */
> +#define HDA_CORB_WP       0x48  /* CORB Write Pointer */ 
> +#define HDA_CORB_RP       0x4A  /* CORB Read Pointer */
> +#define HDA_CORB_CNTRL    0x4C  /* CORB Control */ 
> +#define HDA_CORB_SIZE     0x4E  /* CORB Size */
> +#define HDA_RIRB_LBA      0x50  /* RIRB Lower Base Address */
> +#define HDA_RIRB_UBA      0x54  /* RIRB Upper Base Address */
> +#define HDA_RIRB_WP       0x58  /* RIRB Write Pointer */ 
> +#define HDA_RIRB_RIC      0x5A  /* RIRB Response Interrupt Count */
> +#define HDA_RIRB_CNTRL    0x5C  /* RIRB Control */
> +#define HDA_RIRB_SIZE     0x5E  /* RIRB Size */
> +#define HDA_DMA_PLBA      0x70  /* DMA Position Lower Base Address */
> +#define HDA_DMA_PUBA      0x74  /* DMA Position Upper Base Address */
> +#define HDA_SD_CNTL1      0x00  /* Stream Descriptor */
> +#define HDA_SD_CNTL2      0x01  /* Stream Descriptor */
> +#define HDA_SD_CNTL3      0x02  /* Stream Descriptor */
> +#define HDA_SD_STS        0X03  /* Stream Status */
> +#define HDA_SD_LPIB1      0x04  /* Stream Link Position In Buffer */
> +#define HDA_SD_LPIB2      0x05  /* Stream Link Position In Buffer */
> +#define HDA_SD_LPIB3      0x06  /* Stream Link Position In Buffer */
> +#define HDA_SD_LPIB4      0x07  /* Stream Link Position In Buffer */
> +#define HDA_SD_LVD1       0x0C  /* Stream Last Valid Index */
> +#define HDA_SD_LVD2       0x0D  /* Stream Last Valid Index */
> +#define HDA_SD_FIFOWM1    0x0E  /* Stream FIFO Watermark */ 
> +#define HDA_SD_FIFOWM2    0x0F  /* Stream FIFO Watermark */ 
> +#define HDA_SD_FMT1       0x12  /* Stream Format */
> +#define HDA_SD_FMT2       0x13  /* Stream Format */
> +#endif /* INTEL_HDA_REG*/
> +
> +
> +/* Intel AC97 Registers */
> +
> +#ifndef INTEL_AC97_REG
> +#define AC97_REG
> +#define AC97_RR     0x00  /* Reset Register */
> +#define AC97_MV     0x02  /* Master Valume  */
> +#define AC97_AUX_OV 0x04  /* AUX Output Volume */
> +#define AC97_MPV    0x0E  /* Microphone Valume */
> +#define AC97_PCM_OV 0x18  /* PCM Output Volume  */
> +#define AC97_SRID   0x1A  /* Select Record Input Device */
> +#define AC97_RG     0x1C  /* Record Gain  */
> +#define AC97_RGOM   0x1E  /* Record Gain Of Microphone */
> +#define AC97_GC     0x2C  /* Global Contorl */
> +#define AC97_GS     0x30  /* Global Status  */ 
> +#define AC97_BDBA1  0x00  /* Buffer Descriper Base Address */
> +#define AC97_BDBA2  0x10  /* Buffer Descriper Base Address */
> +#define AC97_BDBA3  0x20  /* Buffer Descriper Base Address */
> +#define AC97_CPSE1  0x04  /* Current Processed Entry */ 
> +#define AC97_CPSE2  0x14  /* Current Processed Entry */
> +#define AC97_CPSE3  0x24  /* Current Processed Entry */
> +#define AC97_LVD1   0x05  /* Last Valid Entry */
> +#define AC97_LVD2   0x15  /* Last Valid Entry */
> +#define AC97_LVD3   0x25  /* Last Valid Entry */
> +#define AC97_TS1    0x06  /* Transfer Status */
> +#define AC97_TS2    0x16  /* Transfer Status */
> +#define AC97_TS3    0x26  /* Transfer Status */
> +#define AC97_PICE1  0x08  /* Position In Current Entry */
> +#define AC97_PICE2  0x18  /* Position In Current Entry */
> +#define AC97_PICE3  0x28  /* Position In Current Entry */
> +#define AC97_PE1    0x0A  /* Prefetched Entry */
> +#define AC97_PE2    0x1A  /* Prefetched Entry */
> +#define AC97_PE3    0x2A  /* Prefetched Entry */
> +#define AC97_TC1    0x0B  /* Transfer Control */
> +#define AC97_TC2    0x1B  /* Transfer Control*/
> +#define AC97_TC3    0x2B  /* Transfer Control*/
> +#endif /* INTEL_AC97_REG */
> +
> +
> +
> +
> +/* Bitwise Functions */
> +
> +#define RESET (1 << 0)
> +#define BLSHIFT(shift,value) (value << shift) /* Left Shifting  */
> +#define BRSHIFT(shift,value) (value >> shift) /* Right Shifting */ 
> +
> +/* Read Functions */
> +
> +#define READ(addrs,offset)(addrs[offset]);
> +
> +/* Write Functions */
> +
> +#define WRITE(addrs,offset,value)(addrs[offset]=value)
> +
> +/* Initalization Funcations */
> +
> +bool init_hda_enge(volatile uint32_t *cntlr);
> +
> +#endif /* HURD_AUDIO_INTERFACE */
> diff --git a/libsound/makefile b/libsound/makefile
> new file mode 100644
> index 00000000..ee5046e5
> --- /dev/null
> +++ b/libsound/makefile
> @@ -0,0 +1,7 @@
> +CC ?= gcc
> +CFLAGS = -Wall -Wextra
> +
> +haudis: audio.o
> +
> +audio.o:
> +     $(CC) -o audio.c 
> -- 
> 2.47.3
> 
> 

-- 
Samuel
 Moralité : le modem et le cablerouteur font comme les filles, ils
 papotent toute la journée.
 -+- RB in NPC : Et en plus, ils ne parlent que de bits -+-

Reply via email to