Hi Hakan,
An update on the high-address work you asked for before revisiting the
trap entry: the kernel now continues bootstrap from the higher-half
alias (KERNEL_MAP_BASE). On QEMU virt with OpenSBI, the version banner
prints from a high VMA (0xffffffff80xxxxxx), so the switch works end
to end.
What changed:
- c_boot_entry() runs at the physical alias, then
riscv64_jump_higher_half() rebases SP/sscratch and jumps to
c_boot_entry_high() — a separate function because the jump needs a
clean frame (the old one points at physical addresses).
- boot_intr_stack (16 KiB) is the interrupt stack published through
sscratch. RISC-V has no hardware stack switch on traps, so trap
entry will swap sp/sscratch and needs a valid kernel stack from the
first instruction.
Before I turn this into patches, one question: does this match the
sscratch/kernel-stack contract you had in mind for the trap entry? My
assumption is that sscratch holds the interrupt stack top while running
on the kernel stack; a trap from userspace swaps sp/sscratch and stores
user regs into the thread's USER_REGS area; traps from kernel mode use
the current stack. If that is the intended scheme, I will rework the
trap entry on top of it.
Thanks,
Diego
