In a makefile like presented in the first response to this issue, it is claimed that it is appropriate for $? to be empty. However, I would assume that if $? is empty and if the target exists, then there is no need to remake the target. Or, to say it the other way around, if an existing target is remade it should be safe to assume $? is non-empty.
Further, the documentation says in 'Rules without Commands or Prerequisites': 'If a rule has no prerequisites or commands, and the target of the rule is a nonexistent file, then make imagines this target to have been updated whenever its rule is run. This implies that all targets depending on this one will always have their commands run.' This, to me, also implies that dependencies like the commonly used FORCE target should be visible in $?. The problem I'm running into with is in the Linux kernel build: When a header file gets moved/deleted and the tree is not cleaned, it is obvious that all objects depending on the no-longer-existing header file need to be re-built (whether this would result in failure is another matter; it doesn't have to since through using multiple include paths it might be possible to find another header that satisfies the source file's needs). For some cases, the build system appears to already work around that issue by also examining $(filter-out FORCE $(wildcard $^),$^), but namely for the compilation of C files this isn't done, and I suppose that it shouldn't be necessary anywhere. Jan _______________________________________________ Bug-make mailing list Bug-make@gnu.org http://lists.gnu.org/mailman/listinfo/bug-make