URL:
<http://savannah.gnu.org/bugs/?17883>
Summary: target-specific variables prevent builtin rules
Project: make
Submitted by: None
Submitted on: Friday 09/29/2006 at 08:30 UTC
Severity: 3 - Normal
Item Group: Bug
Status: None
Privacy: Public
Assigned to: None
Open/Closed: Open
Component Version: 3.81
Operating System: POSIX-Based
Fixed Release: None
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Details:
Hello,
I want to use a Makefile for creating MORE THAN ONE executables from binary
objects from C source files; but each executable has different object files
on which it depends; therefore, instead of a global $(objs) variable (which
works if it were exactly ONE executable, and no target-specific variable were
needed) , I declare a target-specific variable of enumerated object files;
then I instantiate $(objs) in the target prerequisites, possible before OTHER
prerequisites - like "Makefile" -, and call the ${CC} compiler with $(objs)
arguments; but it DOES NOT trigger the builtin rules for %.o targets.
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File Attachments:
-------------------------------------------------------
Date: Friday 09/29/2006 at 08:30 UTC Name: Makefile Size: 2kB By: None
a sample Makefile
<http://savannah.gnu.org/bugs/download.php?file_id=10868>
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<http://savannah.gnu.org/bugs/?17883>
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