Follow-up Comment #1, bug #51495 (project make):
The quick and easy way to accomplish this today is of course to also add the
Makefile to the prerequisites of targets. If you don't want every target to be
rebuilt when only one rule has changed it is also possible to split the
Makefile up into several files with only one rule in each file. Example:
Makefile:
-8<----------------------
all: myprog
include $(wildcard *.mk)
-8<----------------------
link.mk:
-8<----------------------
OBJFILES=file1.o file2.o
LDFLAGS=-lm
myprog: $(OBJFILES) link.mk
gcc -o $@ $(OBJFILES) $(LDFLAGS)
-8<----------------------
compile.mk:
-8<----------------------
CFLAGS=-ansi -pedantic
%.o: %.c compile.mk
gcc -c $(CFLAGS) -o $@ $<
-8<----------------------
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