Follow-up Comment #1, bug #51973 (project make):
This makefile is behaving as defined: when $(call) is used, make performs a
round of variable expansion on the value of the variable that is called. So,
when you say
$(call EXELNK,utl1)
make expands that to
utl1:;@echo "jfh1:pt1::"
This expansion is taking place at the top-level of make parsing and not in the
context of building a target, so there are no target-specific variable
settings to use and $(OBJ1) expands to nothing. Later, when make invokes that
recipe to build the target, it does another round of variable expansion with
the target-specific variables in place...but at that point there are no
variable references left.
In order to have it expand to what you want, you need get the $(OBJ1) variable
reference through the $(call) expansion through to the actual target building.
To do that, double the dollar-sign:
define EXELNK
$(1):;@echo "jfh1:pt1:$$(OBJ1):"
endef
During the expansion of the $(call), the $$ will expand to $ so that the full
rule will be
utl1:;@echo "jfh1:pt1:$(OBJ1):"
...and then when it's invoked as a recipe that target-specific variable
expansion will take place as desired.
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