Update of bug #61171 (project make): Status: None => Not A Bug Open/Closed: Open => Closed
_______________________________________________________ Follow-up Comment #1: I'm not quite sure what the ask is here. The behavior of make in this situation is correct: there is a built-in rule that specifies how to build any file "xxx" from any file "xxx.o", as you discovered. It's standard that every prerequisite is also treated as a target and make will try to update it. If you don't provide a way to update it, then make will use its built-in pattern rules, and of course if it finds a loop in the set of rules it will warn about this. In general this situation is not a problem because it's extremely rare for a source file that gets turned into an object file to be named without any extension. Virtually 100% of the time the source file will be something like "xxx.c" or "xxx.cpp" or similar, not just "xxx". If the question is how to resolve this, you can either remove all built-in rules by adding the -r option to the make command line, or you can cancel this specific built-in rule by adding this to your makefile: % : %.o If you had a newer version of GNU make (the version 3.81 that comes with MacOS is >15 years old and known to contain bugs) you could also set "MAKEFLAGS += -r" inside the makefile to get rid of all built-in rules. _______________________________________________________ Reply to this item at: <https://savannah.gnu.org/bugs/?61171> _______________________________________________ Message sent via Savannah https://savannah.gnu.org/