On Wed, Oct 16, 2019 at 09:15:41PM +1100, Jonathan Gray wrote:
> On Wed, Oct 16, 2019 at 10:42:45AM +0200, Sebastien Marie wrote:
> > On Wed, Oct 16, 2019 at 09:16:41AM +0200, Sebastien Marie wrote:
> >
> > > uvm_fault(0xffffffff82011010, 0x18, 0, 1) -> e
> > > kernel: page fault trap, code=0
> > > Stopped at dc_link_aux_transfer+0x85: movq 0x18(%r14),%rax
> > > ddb{0}> trace
> > > dc_link_aux_transfer(ffff80000013c400,0,ffffffff822db9ad,ffffffff822dbb30,1,0)
> > > at dc_link_aux_transfer+0x85
> > > dm_dp_aux_transfer(ffff800000a838a0,ffffffff822db9a8) at
> > > dm_dp_aux_transfer+0xdc
> > > drm_dp_dpcd_access(ffff800000a838a0,9,0,ffffffff822dbb30,1) at
> > > drm_dp_dpcd_access+0x8d
> > > drm_dp_dpcd_read(ffff800000a838a0,0,ffffffff822dbb30,10) at
> > > drm_dp_dpcd_read+0x45
> > > dm_helpers_dp_read_dpcd(ffff800000a33000,ffff800000a79800,0,ffffffff822dbb30,10)
> > > at dm_helpers_dp_read_dpcd+0x43
> > > core_link_read_dpcd(ffff800000a79800,0,ffffffff822dbb30,10) at
> > > core_link_read_dpcd+0x2d
> > > retrieve_link_cap(ffff800000a79800) at retrieve_link_cap+0x40
> > > dc_link_detect(ffff800000a79800,0) at dc_link_detect+0x99e
> > > dm_hw_init(ffff80000036d000) at dm_hw_init+0xa96
> > > amdgpu_device_init(ffff80000036d000,ffff80000037b000,ffff80000037b018,20016)
> > > at amdgpu_device_init+0x1159
> > > amdgpu_attachhook(ffff80000036d000) at amdgpu_attachhook+0x3b
> > > config_process_deferred_mountroot() at
> > > config_process_deferred_mountroot+0x6b
> > > main(0) at main+0x745
> > > end trace frame: 0x0, count: -13
> >
> > it fails in dc_link_aux_transfer() function, when calling
> > aux_engine->funcs->acquire(aux_engine, ddc_pin)
> > because aux_engine is 0x0.
>
> Try the following, adapted from this linux commit
>
> commit 0e8e4fbf8d8905071c045f2922de55adbe1a6abe
> Author: Hersen Wu <hersenxs...@amd.com>
> Date: Tue Aug 21 09:35:47 2018 -0400
>
It is a big advance: no more crash, and I have working console + xorg (using
amdgpu), even if the display is a bit short for real use.
dmesg section (without DRM_DEBUG):
initializing kernel modesetting (RAVEN 0x1002:0x15DD 0x1002:0x15DD
0xCB).
[drm] *ERROR* construct: Invalid Connector ObjectID from Adapter
Service for connector index:2! type 0 expected 3
amdgpu0: 720x350, 32bpp
Attached:
- dmesg wih DRM_DEBUG
- Xorg.0.log
So the diff is ok semarie@
Thanks.
--
Sebastien Marie
[ 13.107] (WW) checkDevMem: failed to open /dev/xf86 and /dev/mem
(Operation not permitted)
Check that you have set 'machdep.allowaperture=1'
in /etc/sysctl.conf and reboot your machine
refer to xf86(4) for details
[ 13.107] linear framebuffer access unavailable
[ 13.126] (--) Using wscons driver on /dev/ttyC4
[ 13.151]
X.Org X Server 1.20.5
X Protocol Version 11, Revision 0
[ 13.151] Build Operating System: OpenBSD 6.6 amd64
[ 13.151] Current Operating System: OpenBSD olaf.local 6.6 GENERIC.MP#22
amd64
[ 13.151] Build Date: 12 October 2019 11:22:22AM
[ 13.151]
[ 13.151] Current version of pixman: 0.38.4
[ 13.151] Before reporting problems, check http://wiki.x.org
to make sure that you have the latest version.
[ 13.151] Markers: (--) probed, (**) from config file, (==) default setting,
(++) from command line, (!!) notice, (II) informational,
(WW) warning, (EE) error, (NI) not implemented, (??) unknown.
[ 13.151] (==) Log file: "/var/log/Xorg.0.log", Time: Wed Oct 16 13:37:40
2019
[ 13.158] (==) Using system config directory
"/usr/X11R6/share/X11/xorg.conf.d"
[ 13.164] (==) No Layout section. Using the first Screen section.
[ 13.164] (==) No screen section available. Using defaults.
[ 13.164] (**) |-->Screen "Default Screen Section" (0)
[ 13.164] (**) | |-->Monitor "<default monitor>"
[ 13.172] (==) No monitor specified for screen "Default Screen Section".
Using a default monitor configuration.
[ 13.172] (==) Automatically adding devices
[ 13.172] (==) Automatically enabling devices
[ 13.172] (==) Not automatically adding GPU devices
[ 13.173] (==) Max clients allowed: 256, resource mask: 0x1fffff
[ 13.202] (==) FontPath set to:
/usr/X11R6/lib/X11/fonts/misc/,
/usr/X11R6/lib/X11/fonts/TTF/,
/usr/X11R6/lib/X11/fonts/OTF/,
/usr/X11R6/lib/X11/fonts/Type1/,
/usr/X11R6/lib/X11/fonts/100dpi/,
/usr/X11R6/lib/X11/fonts/75dpi/
[ 13.202] (==) ModulePath set to "/usr/X11R6/lib/modules"
[ 13.202] (II) The server relies on wscons to provide the list of input
devices.
If no devices become available, reconfigure wscons or disable
AutoAddDevices.
[ 13.204] (II) Loader magic: 0x1c670ed9000
[ 13.204] (II) Module ABI versions:
[ 13.204] X.Org ANSI C Emulation: 0.4
[ 13.204] X.Org Video Driver: 24.0
[ 13.204] X.Org XInput driver : 24.1
[ 13.204] X.Org Server Extension : 10.0
[ 13.205] (--) PCI:*(56@0:0:0) 1002:15dd:1002:15dd rev 203, Mem @
0xe0000000/268435456, 0xf0000000/2097152, 0xfcc00000/524288, I/O @
0x0000e000/256
[ 13.205] (II) LoadModule: "glx"
[ 13.211] (II) Loading /usr/X11R6/lib/modules/extensions/libglx.so
[ 13.266] (II) Module glx: vendor="X.Org Foundation"
[ 13.266] compiled for 1.20.5, module version = 1.0.0
[ 13.266] ABI class: X.Org Server Extension, version 10.0
[ 13.267] (==) Matched ati as autoconfigured driver 0
[ 13.267] (==) Matched modesetting as autoconfigured driver 1
[ 13.267] (==) Assigned the driver to the xf86ConfigLayout
[ 13.267] (II) LoadModule: "ati"
[ 13.267] (II) Loading /usr/X11R6/lib/modules/drivers/ati_drv.so
[ 13.269] (II) Module ati: vendor="X.Org Foundation"
[ 13.269] compiled for 1.20.5, module version = 19.0.1
[ 13.269] Module class: X.Org Video Driver
[ 13.269] ABI class: X.Org Video Driver, version 24.0
[ 13.294] (II) LoadModule: "amdgpu"
[ 13.294] (II) Loading /usr/X11R6/lib/modules/drivers/amdgpu_drv.so
[ 13.302] (II) Module amdgpu: vendor="X.Org Foundation"
[ 13.302] compiled for 1.20.5, module version = 19.0.1
[ 13.302] Module class: X.Org Video Driver
[ 13.302] ABI class: X.Org Video Driver, version 24.0
[ 13.302] (II) LoadModule: "modesetting"
[ 13.302] (II) Loading /usr/X11R6/lib/modules/drivers/modesetting_drv.so
[ 13.308] (II) Module modesetting: vendor="X.Org Foundation"
[ 13.308] compiled for 1.20.5, module version = 1.20.5
[ 13.308] Module class: X.Org Video Driver
[ 13.308] ABI class: X.Org Video Driver, version 24.0
[ 13.308] (II) AMDGPU: Driver for AMD Radeon:
All GPUs supported by the amdgpu kernel driver
[ 13.308] (II) modesetting: Driver for Modesetting Kernel Drivers: kms
[ 13.337] (II) AMDGPU(0): [KMS] Kernel modesetting enabled.
[ 13.353] (WW) Falling back to old probe method for modesetting
[ 13.354] (II) AMDGPU(0): Creating default Display subsection in Screen
section
"Default Screen Section" for depth/fbbpp 24/32
[ 13.354] (==) AMDGPU(0): Depth 24, (--) framebuffer bpp 32
[ 13.354] (II) AMDGPU(0): Pixel depth = 24 bits stored in 4 bytes (32 bpp
pixmaps)
[ 13.354] (==) AMDGPU(0): Default visual is TrueColor
[ 13.354] (==) AMDGPU(0): RGB weight 888
[ 13.354] (II) AMDGPU(0): Using 8 bits per RGB (8 bit DAC)
[ 13.354] (--) AMDGPU(0): Chipset: "Unknown AMD Radeon GPU" (ChipID = 0x15dd)
[ 13.354] (II) Loading sub module "fb"
[ 13.354] (II) LoadModule: "fb"
[ 13.355] (II) Loading /usr/X11R6/lib/modules/libfb.so
[ 13.359] (II) Module fb: vendor="X.Org Foundation"
[ 13.359] compiled for 1.20.5, module version = 1.0.0
[ 13.359] ABI class: X.Org ANSI C Emulation, version 0.4
[ 13.359] (II) Loading sub module "dri2"
[ 13.359] (II) LoadModule: "dri2"
[ 13.359] (II) Module "dri2" already built-in
[ 14.445] (II) Loading sub module "glamoregl"
[ 14.445] (II) LoadModule: "glamoregl"
[ 14.446] (II) Loading /usr/X11R6/lib/modules/libglamoregl.so
[ 14.479] (II) Module glamoregl: vendor="X.Org Foundation"
[ 14.479] compiled for 1.20.5, module version = 1.0.1
[ 14.479] ABI class: X.Org ANSI C Emulation, version 0.4
[ 14.566] (II) AMDGPU(0): glamor X acceleration enabled on AMD RAVEN (DRM
3.27.0, 6.6, LLVM 8.0.1)
[ 14.566] (II) AMDGPU(0): glamor detected, initialising EGL layer.
[ 14.566] (==) AMDGPU(0): TearFree property default: auto
[ 14.566] (==) AMDGPU(0): VariableRefresh: disabled
[ 14.566] (II) AMDGPU(0): KMS Pageflipping: enabled
[ 14.568] (II) AMDGPU(0): Output HDMI-A-0 has no monitor section
[ 14.568] (II) AMDGPU(0): Output HDMI-A-1 has no monitor section
[ 14.569] (II) AMDGPU(0): Output DisplayPort-0 has no monitor section
[ 14.580] (II) AMDGPU(0): EDID for output HDMI-A-0
[ 14.581] (II) AMDGPU(0): EDID for output HDMI-A-1
[ 14.582] (II) AMDGPU(0): EDID for output DisplayPort-0
[ 14.582] (II) AMDGPU(0): Manufacturer: DEL Model: 3319 Serial#: 808863544
[ 14.582] (II) AMDGPU(0): Year: 1999 Week: 5
[ 14.582] (II) AMDGPU(0): EDID Version: 1.4
[ 14.582] (II) AMDGPU(0): Digital Display Input
[ 14.582] (II) AMDGPU(0): 8 bits per channel
[ 14.582] (II) AMDGPU(0): Digital interface is DisplayPort
[ 14.582] (II) AMDGPU(0): Max Image Size [cm]: horiz.: 28 vert.: 21
[ 14.582] (II) AMDGPU(0): Gamma: 2.28
[ 14.582] (II) AMDGPU(0): DPMS capabilities: StandBy Suspend Off
[ 14.582] (II) AMDGPU(0): Supported color encodings: RGB 4:4:4
[ 14.582] (II) AMDGPU(0): First detailed timing is preferred mode
[ 14.582] (II) AMDGPU(0): Preferred mode is native pixel format and refresh
rate
[ 14.582] (II) AMDGPU(0): redX: 0.625 redY: 0.340 greenX: 0.280 greenY:
0.595
[ 14.582] (II) AMDGPU(0): blueX: 0.150 blueY: 0.063 whiteX: 0.281 whiteY:
0.311
[ 14.582] (II) AMDGPU(0): Supported established timings:
[ 14.582] (II) AMDGPU(0): 720x400@70Hz
[ 14.582] (II) AMDGPU(0): 640x480@60Hz
[ 14.582] (II) AMDGPU(0): 640x480@75Hz
[ 14.582] (II) AMDGPU(0): 800x600@60Hz
[ 14.582] (II) AMDGPU(0): 800x600@75Hz
[ 14.582] (II) AMDGPU(0): 1024x768@60Hz
[ 14.582] (II) AMDGPU(0): 1024x768@75Hz
[ 14.582] (II) AMDGPU(0): Manufacturer's mask: 0
[ 14.582] (II) AMDGPU(0): Supported standard timings:
[ 14.582] (II) AMDGPU(0): #0: hsize: 1024 vsize 768 refresh: 85 vid: 22881
[ 14.582] (II) AMDGPU(0): #1: hsize: 800 vsize 600 refresh: 85 vid: 22853
[ 14.582] (II) AMDGPU(0): #2: hsize: 1280 vsize 1024 refresh: 60 vid:
32897
[ 14.582] (II) AMDGPU(0): #3: hsize: 640 vsize 480 refresh: 85 vid: 22833
[ 14.582] (II) AMDGPU(0): Supported detailed timing:
[ 14.582] (II) AMDGPU(0): clock: 28.3 MHz Image Size: 267 x 200 mm
[ 14.582] (II) AMDGPU(0): h_active: 720 h_sync: 738 h_sync_end 846
h_blank_end 900 h_border: 0
[ 14.582] (II) AMDGPU(0): v_active: 350 v_sync: 388 v_sync_end 390
v_blanking: 449 v_border: 0
[ 14.582] (II) AMDGPU(0): Serial No: 22795C06G819
[ 14.582] (II) AMDGPU(0): Monitor name: DELL 828FI
[ 14.582] (II) AMDGPU(0): Ranges: V min: 50 V max: 120 Hz, H min: 30 H max:
70 kHz,
[ 14.582] (II) AMDGPU(0): EDID (in hex):
[ 14.582] (II) AMDGPU(0): 00ffffffffffff0010ac193338473630
[ 14.582] (II) AMDGPU(0): 05090104a51c1580e00d92a057479826
[ 14.582] (II) AMDGPU(0): 10484fa54a0061594559818031590101
[ 14.582] (II) AMDGPU(0): 010101010101100bd0b4205e6310126c
[ 14.582] (II) AMDGPU(0): 62080bc81000001a000000ff00323237
[ 14.582] (II) AMDGPU(0): 3935433036473831390a000000fc0044
[ 14.582] (II) AMDGPU(0): 454c4c2038323846490a2020000000fd
[ 14.582] (II) AMDGPU(0): 0032781e46ff000a202020202020000f
[ 14.582] (II) AMDGPU(0): Printing probed modes for output DisplayPort-0
[ 14.582] (II) AMDGPU(0): Modeline "720x350"x70.1 28.32 720 738 846 900
350 388 390 449 +hsync -vsync (31.5 kHz eP)
[ 14.582] (II) AMDGPU(0): Modeline "1280x1024"x60.0 108.00 1280 1328 1440
1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz e)
[ 14.582] (II) AMDGPU(0): Modeline "1024x768"x85.0 94.50 1024 1072 1168
1376 768 769 772 808 +hsync +vsync (68.7 kHz e)
[ 14.582] (II) AMDGPU(0): Modeline "1024x768"x75.0 78.75 1024 1040 1136
1312 768 769 772 800 +hsync +vsync (60.0 kHz e)
[ 14.582] (II) AMDGPU(0): Modeline "1024x768"x60.0 65.00 1024 1048 1184
1344 768 771 777 806 -hsync -vsync (48.4 kHz e)
[ 14.582] (II) AMDGPU(0): Modeline "800x600"x85.1 56.25 800 832 896 1048
600 601 604 631 +hsync +vsync (53.7 kHz e)
[ 14.582] (II) AMDGPU(0): Modeline "800x600"x75.0 49.50 800 816 896 1056
600 601 604 625 +hsync +vsync (46.9 kHz e)
[ 14.582] (II) AMDGPU(0): Modeline "800x600"x60.3 40.00 800 840 968 1056
600 601 605 628 +hsync +vsync (37.9 kHz e)
[ 14.582] (II) AMDGPU(0): Modeline "640x480"x85.0 36.00 640 696 752 832
480 481 484 509 -hsync -vsync (43.3 kHz e)
[ 14.582] (II) AMDGPU(0): Modeline "640x480"x75.0 31.50 640 656 720 840
480 481 484 500 -hsync -vsync (37.5 kHz e)
[ 14.582] (II) AMDGPU(0): Modeline "640x480"x59.9 25.18 640 656 752 800
480 490 492 525 -hsync -vsync (31.5 kHz e)
[ 14.582] (II) AMDGPU(0): Modeline "720x400"x70.1 28.32 720 738 846 900
400 412 414 449 -hsync +vsync (31.5 kHz e)
[ 14.582] (II) AMDGPU(0): Output HDMI-A-0 disconnected
[ 14.582] (II) AMDGPU(0): Output HDMI-A-1 disconnected
[ 14.582] (II) AMDGPU(0): Output DisplayPort-0 connected
[ 14.582] (II) AMDGPU(0): Using exact sizes for initial modes
[ 14.582] (II) AMDGPU(0): Output DisplayPort-0 using initial mode 720x350
+0+0
[ 14.582] (II) AMDGPU(0): mem size init: gart size :bfba0000 vram size:
s:7ee75000 visible:7ee75000
[ 14.582] (==) AMDGPU(0): DPI set to (96, 96)
[ 14.582] (==) AMDGPU(0): Using gamma correction (1.0, 1.0, 1.0)
[ 14.582] (II) Loading sub module "ramdac"
[ 14.582] (II) LoadModule: "ramdac"
[ 14.582] (II) Module "ramdac" already built-in
[ 14.582] (II) UnloadModule: "modesetting"
[ 14.582] (II) Unloading modesetting
[ 14.586] (II) AMDGPU(0): [DRI2] Setup complete
[ 14.586] (II) AMDGPU(0): [DRI2] DRI driver: radeonsi
[ 14.586] (II) AMDGPU(0): [DRI2] VDPAU driver: radeonsi
[ 14.588] (II) AMDGPU(0): Front buffer pitch: 3072 bytes
[ 14.594] (II) AMDGPU(0): SYNC extension fences enabled
[ 14.594] (II) AMDGPU(0): Present extension enabled
[ 14.594] (==) AMDGPU(0): DRI3 enabled
[ 14.594] (==) AMDGPU(0): Backing store enabled
[ 14.594] (II) AMDGPU(0): Direct rendering enabled
[ 14.718] (II) AMDGPU(0): Use GLAMOR acceleration.
[ 14.718] (II) AMDGPU(0): Acceleration enabled
[ 14.718] (==) AMDGPU(0): DPMS enabled
[ 14.718] (==) AMDGPU(0): Silken mouse enabled
[ 14.720] (II) AMDGPU(0): Set up textured video (glamor)
[ 14.751] (II) Initializing extension Generic Event Extension
[ 14.753] (II) Initializing extension SHAPE
[ 14.753] (II) Initializing extension MIT-SHM
[ 14.754] (II) Initializing extension XInputExtension
[ 14.755] (II) Initializing extension XTEST
[ 14.756] (II) Initializing extension BIG-REQUESTS
[ 14.756] (II) Initializing extension SYNC
[ 14.757] (II) Initializing extension XKEYBOARD
[ 14.759] (II) Initializing extension XC-MISC
[ 14.760] (II) Initializing extension SECURITY
[ 14.760] (II) Initializing extension XFIXES
[ 14.761] (II) Initializing extension RENDER
[ 14.761] (II) Initializing extension RANDR
[ 14.762] (II) Initializing extension COMPOSITE
[ 14.763] (II) Initializing extension DAMAGE
[ 14.763] (II) Initializing extension MIT-SCREEN-SAVER
[ 14.764] (II) Initializing extension DOUBLE-BUFFER
[ 14.765] (II) Initializing extension RECORD
[ 14.766] (II) Initializing extension DPMS
[ 14.766] (II) Initializing extension Present
[ 14.767] (II) Initializing extension DRI3
[ 14.767] (II) Initializing extension X-Resource
[ 14.768] (II) Initializing extension XVideo
[ 14.768] (II) Initializing extension XVideo-MotionCompensation
[ 14.768] (II) Initializing extension GLX
[ 14.774] (II) AIGLX: Loaded and initialized radeonsi
[ 14.774] (II) GLX: Initialized DRI2 GL provider for screen 0
[ 14.774] (II) Initializing extension XFree86-VidModeExtension
[ 14.775] (II) Initializing extension XFree86-DGA
[ 14.775] (II) Initializing extension XFree86-DRI
[ 14.777] (II) Initializing extension DRI2
[ 14.784] (II) AMDGPU(0): Setting screen physical size to 190 x 92
[ 15.098] (II) config/wscons: checking input device /dev/wskbd
[ 15.098] (II) wskbd: using layout fr
[ 15.098] (II) LoadModule: "kbd"
[ 15.098] (II) Loading /usr/X11R6/lib/modules/input/kbd_drv.so
[ 15.099] (II) Module kbd: vendor="X.Org Foundation"
[ 15.099] compiled for 1.20.5, module version = 1.9.0
[ 15.099] Module class: X.Org XInput Driver
[ 15.099] ABI class: X.Org XInput driver, version 24.1
[ 15.099] (II) Using input driver 'kbd' for '/dev/wskbd'
[ 15.099] (**) /dev/wskbd: always reports core events
[ 15.099] (**) /dev/wskbd: always reports core events
[ 15.099] (**) Option "Protocol" "standard"
[ 15.099] (**) Option "XkbRules" "base"
[ 15.099] (**) Option "XkbModel" "pc105"
[ 15.099] (**) Option "XkbLayout" "fr"
[ 15.099] (II) XINPUT: Adding extended input device "/dev/wskbd" (type:
KEYBOARD, id 6)
[ 15.152] (II) config/wscons: checking input device /dev/wsmouse
[ 15.152] (II) LoadModule: "ws"
[ 15.153] (II) Loading /usr/X11R6/lib/modules/input/ws_drv.so
[ 15.154] (II) Module ws: vendor="X.Org Foundation"
[ 15.154] compiled for 1.20.5, module version = 1.3.0
[ 15.154] Module class: X.Org XInput Driver
[ 15.154] ABI class: X.Org XInput driver, version 24.1
[ 15.154] (II) Using input driver 'ws' for '/dev/wsmouse'
[ 15.154] (**) /dev/wsmouse: always reports core events
[ 15.154] (II) ws: /dev/wsmouse: debuglevel 0
[ 15.154] (**) Option "Device" "/dev/wsmouse"
[ 15.154] (**) ws: /dev/wsmouse: ZAxisMapping: buttons 4 and 5
[ 15.154] (**) ws: /dev/wsmouse: WAxisMapping: buttons 6 and 7
[ 15.154] (**) ws: /dev/wsmouse: associated screen: 0
[ 15.154] (EE) PreInit returned 2 for "/dev/wsmouse"
[ 15.154] (II) UnloadModule: "ws"
>> OpenBSD/amd64 BOOT 3.45
boot>
booting hd0a:/bsd: 12866888+3064848+340000+0+708608
[8086642+1054056+220+762272]=0x19a6220
entry point at 0xffffffff81001000
[ using 9904672 bytes of bsd ELF symbol table ]
Copyright (c) 1982, 1986, 1989, 1991, 1993
The Regents of the University of California. All rights reserved.
Copyright (c) 1995-2019 OpenBSD. All rights reserved. https://www.OpenBSD.org
OpenBSD 6.6-current (GENERIC.MP) #21: Wed Oct 16 13:29:39 CEST 2019
semarie@olaf.local:/home/semarie/sys/arch/amd64/compile/GENERIC.MP
real mem = 14941466624 (14249MB)
avail mem = 14468730880 (13798MB)
mpath0 at root
scsibus0 at mpath0: 256 targets
mainbus0 at root
bios0 at mainbus0: SMBIOS rev. 3.2 @ 0xe6cc0 (23 entries)
bios0: vendor American Megatrends Inc. version "P2.00" date 03/04/2019
bios0: ASRock A320M-HDV R4.0
acpi0 at bios0: ACPI 6.0
acpi0: sleep states S0 S4 S5
acpi0: tables DSDT FACP APIC FPDT FIDT SSDT SSDT SSDT MCFG AAFT HPET UEFI SSDT
CRAT CDIT SSDT SSDT WSMT SSDT
acpi0: wakeup devices GPP0(S4) GPP2(S4) GPP3(S4) GPP4(S4) GPP5(S4) GPP6(S4)
GP17(S4) XHC0(S4) XHC1(S4) GP18(S4) PS2K(S4) GPP1(S4) PTXH(S4)
acpitimer0 at acpi0: 3579545 Hz, 32 bits
acpimadt0 at acpi0 addr 0xfee00000: PC-AT compat
cpu0 at mainbus0: apid 0 (boot processor)
cpu0: AMD Athlon 220GE with Radeon Vega Graphics, 3394.22 MHz, 17-11-00
cpu0:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,RDSEED,ADX,SMAP,CLFLUSHOPT,SHA,IBPB,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
cpu0: 64KB 64b/line 4-way I-cache, 32KB 64b/line 8-way D-cache, 512KB 64b/line
8-way L2 cache, 4MB 64b/line 16-way L3 cache
cpu0: ITLB 64 4KB entries fully associative, 64 4MB entries fully associative
cpu0: DTLB 64 4KB entries fully associative, 64 4MB entries fully associative
cpu0: smt 0, core 0, package 0
mtrr: Pentium Pro MTRR support, 8 var ranges, 88 fixed ranges
cpu0: apic clock running at 24MHz
cpu0: mwait min=64, max=64, C-substates=1.1, IBE
cpu1 at mainbus0: apid 1 (application processor)
cpu1: AMD Athlon 220GE with Radeon Vega Graphics, 3393.59 MHz, 17-11-00
cpu1:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,RDSEED,ADX,SMAP,CLFLUSHOPT,SHA,IBPB,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
cpu1: 64KB 64b/line 4-way I-cache, 32KB 64b/line 8-way D-cache, 512KB 64b/line
8-way L2 cache, 4MB 64b/line 16-way L3 cache
cpu1: ITLB 64 4KB entries fully associative, 64 4MB entries fully associative
cpu1: DTLB 64 4KB entries fully associative, 64 4MB entries fully associative
cpu1: smt 0, core 1, package 0
ioapic0 at mainbus0: apid 3 pa 0xfec00000, version 21, 24 pins
ioapic1 at mainbus0: apid 4 pa 0xfec01000, version 21, 32 pins
acpimcfg0 at acpi0
acpimcfg0: addr 0xf8000000, bus 0-63
acpihpet0 at acpi0: 14318180 Hz
acpiprt0 at acpi0: bus 0 (PCI0)
acpiprt1 at acpi0: bus -1 (GPP0)
acpiprt2 at acpi0: bus -1 (GPP2)
acpiprt3 at acpi0: bus -1 (GPP3)
acpiprt4 at acpi0: bus -1 (GPP4)
acpiprt5 at acpi0: bus -1 (GPP5)
acpiprt6 at acpi0: bus -1 (GPP6)
acpiprt7 at acpi0: bus 56 (GP17)
acpiprt8 at acpi0: bus 57 (GP18)
acpiprt9 at acpi0: bus 21 (GPP1)
acpicpu0 at acpi0: C2(0@400 io@0x414), C1(0@1 mwait), PSS
acpicpu1 at acpi0: C2(0@400 io@0x414), C1(0@1 mwait), PSS
acpipci0 at acpi0 PCI0: 0x00000010 0x00000011 0x00000000
acpicmos0 at acpi0
acpibtn0 at acpi0: PWRB
"AMDI0030" at acpi0 not configured
"AMDIF030" at acpi0 not configured
"PNP0C14" at acpi0 not configured
acpivideo0 at acpi0: VGA_
acpivideo1 at acpi0: VGA_
cpu0: 3394 MHz: speeds: 3400 2300 1600 MHz
pci0 at mainbus0 bus 0
ksmn0 at pci0 dev 0 function 0 "AMD AMD64 17h/1xh Root Complex" rev 0x00
pchb0 at pci0 dev 1 function 0 "AMD AMD64 17h PCIE" rev 0x00
ppb0 at pci0 dev 1 function 2 "AMD AMD64 17h/1xh PCIE" rev 0x00: msi
pci1 at ppb0 bus 21
xhci0 at pci1 dev 0 function 0 vendor "AMD", unknown product 0x43bc rev 0x02:
msi, xHCI 1.10
usb0 at xhci0: USB revision 3.0
uhub0 at usb0 configuration 1 interface 0 "AMD xHCI root hub" rev 3.00/1.00
addr 1
ahci0 at pci1 dev 0 function 1 vendor "AMD", unknown product 0x43b8 rev 0x02:
msi, AHCI 1.3.1
ahci0: port busy after first PMP probe FIS
ahci0: port busy after first PMP probe FIS
ahci0: port 0: 6.0Gb/s
scsibus1 at ahci0: 32 targets
sd0 at scsibus1 targ 0 lun 0: <ATA, LDLC, R083> t10.ATA_LDLC_03302219C0199_
sd0: 228936MB, 512 bytes/sector, 468862128 sectors, thin
ppb1 at pci1 dev 0 function 2 vendor "AMD", unknown product 0x43b3 rev 0x02
pci2 at ppb1 bus 22
ppb2 at pci2 dev 4 function 0 "AMD 300 Series PCIE" rev 0x02: msi
pci3 at ppb2 bus 27
ppb3 at pci2 dev 6 function 0 "AMD 300 Series PCIE" rev 0x02: msi
pci4 at ppb3 bus 29
ppb4 at pci2 dev 7 function 0 "AMD 300 Series PCIE" rev 0x02: msi
pci5 at ppb4 bus 30
re0 at pci5 dev 0 function 0 "Realtek 8168" rev 0x15: RTL8168H/8111H (0x5400),
msi, address 70:85:c2:d6:76:a4
rgephy0 at re0 phy 7: RTL8251 PHY, rev. 0
pchb1 at pci0 dev 8 function 0 "AMD AMD64 17h PCIE" rev 0x00
ppb5 at pci0 dev 8 function 1 "AMD AMD64 17h/1xh PCIE" rev 0x00
pci6 at ppb5 bus 56
amdgpu0 at pci6 dev 0 function 0 "ATI Radeon Vega" rev 0xcb
drm0 at amdgpu0
amdgpu0: msi
azalia0 at pci6 dev 0 function 1 "ATI Radeon Vega HD Audio" rev 0x00: msi
azalia0: no supported codecs
ccp0 at pci6 dev 0 function 2 "AMD AMD64 17h/1xh Crypto" rev 0x00
xhci1 at pci6 dev 0 function 3 "AMD AMD64 17h/1xh xHCI" rev 0x00: msi, xHCI 1.10
usb1 at xhci1: USB revision 3.0
uhub1 at usb1 configuration 1 interface 0 "AMD xHCI root hub" rev 3.00/1.00
addr 1
xhci2 at pci6 dev 0 function 4 "AMD AMD64 17h/1xh xHCI" rev 0x00: msi, xHCI 1.10
usb2 at xhci2: USB revision 3.0
uhub2 at usb2 configuration 1 interface 0 "AMD xHCI root hub" rev 3.00/1.00
addr 1
azalia1 at pci6 dev 0 function 6 "AMD AMD64 17h/1xh HD Audio" rev 0x00: apic 4
int 30
azalia1: codecs: Realtek/0x0887
audio0 at azalia1
ppb6 at pci0 dev 8 function 2 "AMD AMD64 17h/1xh PCIE" rev 0x00
pci7 at ppb6 bus 57
ahci1 at pci7 dev 0 function 0 "AMD FCH AHCI" rev 0x61: msi, AHCI 1.3.1
scsibus2 at ahci1: 32 targets
"AMD FCH SMBus" rev 0x61 at pci0 dev 20 function 0 not configured
pcib0 at pci0 dev 20 function 3 "AMD FCH LPC" rev 0x51
pchb2 at pci0 dev 24 function 0 "AMD AMD64 17h/1xh Data Fabric" rev 0x00
pchb3 at pci0 dev 24 function 1 "AMD AMD64 17h/1xh Data Fabric" rev 0x00
pchb4 at pci0 dev 24 function 2 "AMD AMD64 17h/1xh Data Fabric" rev 0x00
pchb5 at pci0 dev 24 function 3 "AMD AMD64 17h/1xh Data Fabric" rev 0x00
pchb6 at pci0 dev 24 function 4 "AMD AMD64 17h/1xh Data Fabric" rev 0x00
pchb7 at pci0 dev 24 function 5 "AMD AMD64 17h/1xh Data Fabric" rev 0x00
pchb8 at pci0 dev 24 function 6 "AMD AMD64 17h/1xh Data Fabric" rev 0x00
pchb9 at pci0 dev 24 function 7 "AMD AMD64 17h/1xh Data Fabric" rev 0x00
isa0 at pcib0
isadma0 at isa0
com0 at isa0 port 0x3f8/8 irq 4: ns16550a, 16 byte fifo
com0: console
pckbc0 at isa0 port 0x60/5 irq 1 irq 12
pckbd0 at pckbc0 (kbd slot)
wskbd0 at pckbd0: console keyboard
pcppi0 at isa0 port 0x61
spkr0 at pcppi0
vmm0 at mainbus0: SVM/RVI
vscsi0 at root
scsibus3 at vscsi0: 256 targets
softraid0 at root
scsibus4 at softraid0: 256 targets
root on sd0a (6bb7ffab3d187e8c.a) swap on sd0b dump on sd0b
initializing kernel modesetting (RAVEN 0x1002:0x15DD 0x1002:0x15DD 0xCB).
[drm] register mmio base: 0xFCC00000
[drm] register mmio size: 524288
[drm] probing pcie caps for device 56:0:0 0x1002:0x15dd = 3/e
[drm] probing pcie caps for device 0:8:1 0x1022:0x15db = 3/e
[drm] probing pcie width for device 0:8:1 0x1022:0x15db = 700d03
[drm] add ip block number 0 <soc15_common>
[drm] add ip block number 1 <gmc_v9_0>
[drm] add ip block number 2 <vega10_ih>
[drm] add ip block number 3 <psp>
[drm] add ip block number 4 <powerplay>
[drm] add ip block number 5 <dm>
[drm] add ip block number 6 <gfx_v9_0>
[drm] add ip block number 7 <sdma_v4_0>
[drm] add ip block number 8 <vcn_v1_0>
[drm] VCN decode is enabled in VM mode
[drm] VCN encode is enabled in VM mode
[drm] VCN jpeg decode is enabled in VM mode
[drm] BIOS signature incorrect 20 7
[drm] BIOS signature incorrect 20 7
[drm] vm size is 262144 GB, 4 levels, block size is 9-bit, fragment size is
9-bit
drm: VRAM: 2048M 0x000000F400000000 - 0x000000F47FFFFFFF (2048M used)
drm: GART: 1024M 0x000000F500000000 - 0x000000F53FFFFFFF
[drm] Detected VRAM RAM=2048M, BAR=2048M
[drm] RAM width 64bits DDR4
[drm] GART: num cpu pages 262144, num gpu pages 262144
drm:pid0:amdgpu_fence_driver_start_ring *DEBUG* fence driver on ring 0 use gpu
addr 0x000000f500400040, cpu addr 0x0xfffffd83ae7eb040
drm:pid0:amdgpu_fence_driver_start_ring *DEBUG* fence driver on ring 1 use gpu
addr 0x000000f5004000c0, cpu addr 0x0xfffffd83ae7eb0c0
drm:pid0:amdgpu_fence_driver_start_ring *DEBUG* fence driver on ring 2 use gpu
addr 0x000000f500400140, cpu addr 0x0xfffffd83ae7eb140
drm:pid0:amdgpu_fence_driver_start_ring *DEBUG* fence driver on ring 3 use gpu
addr 0x000000f5004001c0, cpu addr 0x0xfffffd83ae7eb1c0
drm:pid0:amdgpu_fence_driver_start_ring *DEBUG* fence driver on ring 4 use gpu
addr 0x000000f500400240, cpu addr 0x0xfffffd83ae7eb240
drm:pid0:amdgpu_fence_driver_start_ring *DEBUG* fence driver on ring 5 use gpu
addr 0x000000f5004002c0, cpu addr 0x0xfffffd83ae7eb2c0
drm:pid0:amdgpu_fence_driver_start_ring *DEBUG* fence driver on ring 6 use gpu
addr 0x000000f500400340, cpu addr 0x0xfffffd83ae7eb340
drm:pid0:amdgpu_fence_driver_start_ring *DEBUG* fence driver on ring 7 use gpu
addr 0x000000f5004003c0, cpu addr 0x0xfffffd83ae7eb3c0
drm:pid0:amdgpu_fence_driver_start_ring *DEBUG* fence driver on ring 8 use gpu
addr 0x000000f500400440, cpu addr 0x0xfffffd83ae7eb440
drm:pid0:amdgpu_fence_driver_start_ring *DEBUG* fence driver on ring 9 use gpu
addr 0x000000f5004004e0, cpu addr 0x0xfffffd83ae7eb4e0
[drm] use_doorbell being set to: [true]
drm:pid0:amdgpu_fence_driver_start_ring *DEBUG* fence driver on ring 10 use gpu
addr 0x000000f500400560, cpu addr 0x0xfffffd83ae7eb560
[drm] Found VCN firmware Version: 1.73 Family ID: 18
[drm] PSP loading VCN firmware
drm:pid0:amdgpu_fence_driver_start_ring *DEBUG* fence driver on ring 11 use gpu
addr 0x000000f5004005e0, cpu addr 0x0xfffffd83ae7eb5e0
drm:pid0:amdgpu_fence_driver_start_ring *DEBUG* fence driver on ring 12 use gpu
addr 0x000000f500400660, cpu addr 0x0xfffffd83ae7eb660
drm:pid0:amdgpu_fence_driver_start_ring *DEBUG* fence driver on ring 13 use gpu
addr 0x000000f5004006e0, cpu addr 0x0xfffffd83ae7eb6e0
drm:pid0:amdgpu_fence_driver_start_ring *DEBUG* fence driver on ring 14 use gpu
addr 0x000000f500400760, cpu addr 0x0xfffffd83ae7eb760
[drm] DM_IRQ
[drm] Don't have set_crtc_timing for v1
[drm] DM_PPLIB: values for Invalid clock
[drm] DM_PPLIB: 400000 in kHz
[drm] DM_PPLIB: 933000 in kHz
[drm] DM_PPLIB: 1200000 in kHz
[drm] DM_PPLIB: 1333000 in kHz
[drm] DM_PPLIB: values for Invalid clock
[drm] DM_PPLIB: 300000 in kHz
[drm] DM_PPLIB: 600000 in kHz
[drm] DM_PPLIB: 626000 in kHz
[drm] DM_PPLIB: 654000 in kHz
[BANDWIDTH_CALCS]:sr_exit_time: f ns
sr_enter_plus_exit_time: f ns
urgent_latency: f ns
write_back_latency: f ns
percent_of_ideal_drambw_received_after_urg_latency: f %
max_request_size: 256 bytes
dcfclkv_max0p9: f kHz
dcfclkv_nom0p8: f kHz
dcfclkv_mid0p72: f kHz
dcfclkv_min0p65: f kHz
max_dispclk_vmax0p9: f kHz
max_dispclk_vnom0p8: f kHz
max_dispclk_vmid0p72: f kHz
max_dispclk_vmin0p65: f kHz
max_dppclk_vmax0p9: f kHz
max_dppclk_vnom0p8: f kHz
max_dppclk_vmid0p72: f kHz
max_dppclk_vmin0p65: f kHz
socclk: f kHz
fabric_and_dram_bandwidth_vmax0p9: f MB/s
fabric_and_dram_bandwidth_vnom0p8: f MB/s
fabric_and_dram_bandwidth_vmid0p72: f MB/s
fabric_and_dram_bandwidth_vmin0p65: f MB/s
phyclkv_max0p9: f kHz
phyclkv_nom0p8: f kHz
phyclkv_mid0p72: f kHz
phyclkv_min0p65: f kHz
downspreading: f %
round_trip_ping_latency_cycles: 128 DCFCLK Cycles
urgent_out_of_order_return_per_channel: 256 Bytes
number_of_channels: 1
vmm_page_size: 4096 Bytes
dram_clock_change_latency: f ns
return_bus_width: 0 Bytes
[BANDWIDTH_CALCS]:rob_buffer_size_in_kbyte: f
det_buffer_size_in_kbyte: f
dpp_output_buffer_pixels: f
opp_output_buffer_lines: f
pixel_chunk_size_in_kbyte: f
pte_enable: 6
pte_chunk_size: 2 kbytes
meta_chunk_size: 2 kbytes
writeback_chunk_size: 2 kbytes
odm_capability: 13
dsc_capability: 13
line_buffer_size: 589824 bits
max_line_buffer_lines: 12
is_line_buffer_bpp_fixed: 13
line_buffer_fixed_bpp: 39
writeback_luma_buffer_size: 12 kbytes
writeback_chroma_buffer_size: 8 kbytes
max_num_dpp: 4
max_num_writeback: 2
max_dchub_topscl_throughput: 4 pixels/dppclk
max_pscl_tolb_throughput: 2 pixels/dppclk
max_lb_tovscl_throughput: 4 pixels/dppclk
max_vscl_tohscl_throughput: 4 pixels/dppclk
max_hscl_ratio: f
max_vscl_ratio: f
max_hscl_taps: 8
max_vscl_taps: 8
pte_buffer_size_in_requests: 42
dispclk_ramping_margin: f %
under_scan_factor: f %
max_inter_dcn_tile_repeaters: 0
can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one: 8
bug_forcing_luma_and_chroma_request_to_same_size_fixed: 13
dcfclk_cstate_latency: 13
[HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 86 data: 408289520
[HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 86 data: 408289520
[HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 86 data: 408289520
[HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 86 data: 408289520
[drm] DC: create_links: connectors_num: physical:4, virtual:0
[drm] Connector[0] description:signal 4
[drm] Connector[1] description:signal 4
[drm] *ERROR* construct: Invalid Connector ObjectID from Adapter Service for
connector index:2! type 0 expected 3
[drm] Connector[3] description:signal 32
[drm] Power gated front end 0
[drm] Power down front end 0
[drm] Power gated front end 1
[drm] Power down front end 1
[drm] Power gated front end 2
[drm] Power down front end 2
[HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 84 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 84 data: 1
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 84 data: 0
[drm] Display Core initialized
[drm] Display Core initialized with v3.1.59!
[drm] amdgpu: freesync_module init done 0xffff80000065ed80.
[drm] amdgpu_dm_connector_init()
[drm] link=0, dc_sink_in=0x0 is now Disconnected prev_sink=0x0 dpcd same=1 edid
same=0
[drm] DCHPD: connector_id=0: dc_sink didn't change.
[drm] amdgpu_dm_connector_init()
[drm] link=1, dc_sink_in=0x0 is now Disconnected prev_sink=0x0 dpcd same=1 edid
same=0
[drm] DCHPD: connector_id=1: dc_sink didn't change.
[drm] amdgpu_dm_connector_init()
[drm] 11 [drm] 0A [drm] 82 [drm] 01 [drm] 00 [drm] 03 [drm] 01 [drm] 81 [drm]
00 [drm] 00 [drm] 00 [drm] 00 [drm] 00 [drm] 00 [drm] 00 [drm] 00 [drm] Rx
Caps: [drm] SAD: no CEA Extension found
[drm] SADs count is: -2, don't need to read it
[BIOS]:transmitter_control_v1_6:ps.param.symclk_10khz = 27000
[HW_LINK_TRAINING]:dpcd_set_link_settings
100 rate = a
101 lane = 2
107 spread = 10
[HW_LINK_TRAINING]:dpcd_set_lt_pattern_and_lane_settings
102 pattern = 1
[HW_LINK_TRAINING]:dpcd_set_lt_pattern_and_lane_settings:
103 VS set = 0 PE set = 0 max VS Reached = 0 max PE Reached = 0
[HW_LINK_TRAINING]:wait_for_training_aux_rd_interval:
wait = 100
[HW_LINK_TRAINING]:get_lane_status_and_drive_settings:
202 Lane01Status = 11
203 Lane23Status = 0
[HW_LINK_TRAINING]:get_lane_status_and_drive_settings:
206 Lane01AdjustRequest = 0
207 Lane23AdjustRequest = 0
[HW_LINK_TRAINING]:dpcd_set_lt_pattern_and_lane_settings
102 pattern = 2
[HW_LINK_TRAINING]:dpcd_set_lt_pattern_and_lane_settings:
103 VS set = 0 PE set = 0 max VS Reached = 0 max PE Reached = 0
[HW_LINK_TRAINING]:wait_for_training_aux_rd_interval:
wait = 400
[HW_LINK_TRAINING]:get_lane_status_and_drive_settings:
202 Lane01Status = 77
203 Lane23Status = 0
[HW_LINK_TRAINING]:get_lane_status_and_drive_settings:
206 Lane01AdjustRequest = 0
207 Lane23AdjustRequest = 0
[HW_LINK_TRAINING]:dpcd_set_training_pattern
102 pattern = 0
[drm] HBRx2 pass VS=0, PE=0[drm] 00 [drm] FF [drm] FF [drm] FF [drm] FF [drm]
FF [drm] FF [drm] 00 [drm] 10 [drm] AC [drm] 19 [drm] 33 [drm] 38 [drm] 47
[drm] 36 [drm] 30 [drm] 05 [drm] 09 [drm] 01 [drm] 04 [drm] A5 [drm] 1C [drm]
15 [drm] 80 [drm] E0 [drm] 0D [drm] 92 [drm] A0 [drm] 57 [drm] 47 [drm] 98
[drm] 26 [drm] 10 [drm] 48 [drm] 4F [drm] A5 [drm] 4A [drm] 00 [drm] 61 [drm]
59 [drm] 45 [drm] 59 [drm] 81 [drm] 80 [drm] 31 [drm] 59 [drm] 01 [drm] 01
[drm] 01 [drm] 01 [drm] 01 [drm] 01 [drm] 01 [drm] 01 [drm] 10 [drm] 0B [drm]
D0 [drm] B4 [drm] 20 [drm] 5E [drm] 63 [drm] 10 [drm] 12 [drm] 6C [drm] 62
[drm] 08 [drm] 0B [drm] C8 [drm] 10 [drm] 00 [drm] 00 [drm] 1A [drm] 00 [drm]
00 [drm] 00 [drm] FF [drm] 00 [drm] 32 [drm] 32 [drm] 37 [drm] 39 [drm] 35
[drm] 43 [drm] 30 [drm] 36 [drm] 47 [drm] 38 [drm] 31 [drm] 39 [drm] 0A [drm]
00 [drm] 00 [drm] 00 [drm] FC [drm] 00 [drm] 44 [drm] 45 [drm] 4C [drm] 4C
[drm] 20 [drm] 38 [drm] 32 [drm] 38 [drm] 46 [drm] 49 [drm] 0A [drm] 20 [drm]
20 [drm] 00 [drm] 00 [drm] 00 [drm] FD [drm] 00 [drm] 32 [drm] 78 [drm] 1E
[drm] 46 [drm] FF [drm] 00 [drm] 0A [drm] 20 [drm] 20 [drm] 20 [drm] 20 [drm]
20 [drm] 20 [drm] 00 [drm] 0F [drm] DELL 828FI: [Block 0] [drm] dc_link_detect:
manufacturer_id = AC10, product_id = 3319, serial_number = 30364738,
manufacture_week = 5, manufacture_year = 9, display_name = DELL 828FI,
speaker_flag = 0, audio_mode_count = 0
[drm] link=2, dc_sink_in=0xffff800000120c00 is now Connected prev_sink=0x0 dpcd
same=1 edid same=0
[drm] DCHPD: connector_id=2: Old sink=0x0 New sink=0xffff800000120c00
[drm] non_desktop set to 0
[drm] DM_IRQ: added irq handler: 0xffff80000065e380 for: dal_src=78, irq
context=1
[drm] DM_IRQ: added irq handler: 0xffff80000065e440 for: dal_src=79, irq
context=1
[drm] DM_IRQ: added irq handler: 0xffff80000065e500 for: dal_src=80, irq
context=1
[drm] DM_IRQ: added irq handler: 0xffff80000065e5c0 for: dal_src=81, irq
context=1
[drm] DM_IRQ: added irq handler: 0xffff80000065e680 for: dal_src=26, irq
context=1
[drm] DM_IRQ: added irq handler: 0xffff80000065e700 for: dal_src=27, irq
context=1
[drm] DM_IRQ: added irq handler: 0xffff80000065e780 for: dal_src=28, irq
context=1
[drm] DM_IRQ: added irq handler: 0xffff80000065e2c0 for: dal_src=29, irq
context=1
[drm] DM_IRQ: added irq handler: 0xffff80000065e300 for: dal_src=1, irq
context=0
[drm] DM_IRQ: added irq handler: 0xffff80000065e340 for: dal_src=2, irq
context=0
[drm] DM_IRQ: added irq handler: 0xffff800000719000 for: dal_src=4, irq
context=0
[drm] DM_IRQ: added irq handler: 0xffff800000719040 for: dal_src=10, irq
context=0
[drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[drm] Driver supports precise vblank timestamp query.
[drm] KMS initialized.
[drm] VCN decode and encode initialized successfully.
[drm]
[drm] [CONNECTOR:47:HDMI-A-]
[drm] [CONNECTOR:47:HDMI-A-] status updated from unknown to disconnected
[drm] [CONNECTOR:47:HDMI-A-] disconnected
[drm] [CONNECTOR:49:HDMI-A-]
[drm] [CONNECTOR:49:HDMI-A-] status updated from unknown to disconnected
[drm] [CONNECTOR:49:HDMI-A-] disconnected
[drm] [CONNECTOR:51:DP-]
[drm] [CONNECTOR:51:DP-] status updated from unknown to connected
[drm] Finding the best encoder
[drm] ELD: no CEA Extension found
[drm] non_desktop set to 0
[drm] Finding the best encoder
[drm] Destination Rectangle x:0 y:0 width:720 height:350
[drm] Destination Rectangle x:0 y:0 width:1024 height:768
[drm] Destination Rectangle x:0 y:0 width:800 height:600
[drm] Destination Rectangle x:0 y:0 width:1280 height:1024
[drm] Destination Rectangle x:0 y:0 width:640 height:480
[drm] Destination Rectangle x:0 y:0 width:800 height:600
[drm] Destination Rectangle x:0 y:0 width:640 height:480
[drm] Destination Rectangle x:0 y:0 width:640 height:480
[drm] Destination Rectangle x:0 y:0 width:720 height:400
[drm] Destination Rectangle x:0 y:0 width:1024 height:768
[drm] Destination Rectangle x:0 y:0 width:1024 height:768
[drm] Destination Rectangle x:0 y:0 width:800 height:600
[drm] [CONNECTOR:51:DP-] probed modes :
[drm] Modeline 53:"720x350" 70 28320 720 738 846 900 350 388 390 449 0x48 0x9
[drm] Modeline 56:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066
0x40 0x5
[drm] Modeline 54:"1024x768" 85 94500 1024 1072 1168 1376 768 769 772 808 0x40
0x5
[drm] Modeline 62:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40
0x5
[drm] Modeline 63:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40
0xa
[drm] Modeline 55:"800x600" 85 56250 800 832 896 1048 600 601 604 631 0x40 0x5
[drm] Modeline 64:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
[drm] Modeline 58:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
[drm] Modeline 57:"640x480" 85 36000 640 696 752 832 480 481 484 509 0x40 0xa
[drm] Modeline 59:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
[drm] Modeline 60:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
[drm] Modeline 61:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
[drm] connector 47 enabled? no
[drm] connector 49 enabled? no
[drm] connector 51 enabled? yes
[drm] looking for cmdline mode on connector 51
[drm] looking for preferred mode on connector 51 0
[drm] found mode 720x350
[drm] picking CRTCs for 16384x16384 config
[drm] desired mode 720x350 set on crtc 41 (0,0)
[drm] vram apper at 0x60000000
[drm] size 1081344
[drm] fb depth is 24
[drm] pitch is 3072
[drm] Call to ATCS verify_interface failed: -5
[drm] No ATIF handle found
drm:pid0:amdgpu_attachhook *DEBUG* Error during ACPI methods call
[drm] Finding the best encoder
[drm] Finding the best encoder
[drm] amdgpu_crtc id:0 crtc_state_flags: enable:1, active:1, planes_changed:0,
mode_changed:1,active_changed:1,connectors_changed:1
[drm] Destination Rectangle x:0 y:0 width:720 height:350
[drm] amdgpu_crtc id:0 crtc_state_flags: enable:1, active:1, planes_changed:0,
mode_changed:1,active_changed:1,connectors_changed:1
[drm] Enabling DRM crtc: 41
[drm] Enabling DRM plane: 39 on DRM crtc 41
[SCALER]:resource_build_scaling_params: Viewport:
height:350 width:720 x:0 y:0
dst_rect:
height:350 width:720 x:0 y:0
[SCALER]:resource_build_scaling_params: Viewport:
height:350 width:360 x:0 y:0
dst_rect:
height:350 width:720 x:0 y:0
[SCALER]:resource_build_scaling_params: Viewport:
height:350 width:360 x:360 y:0
dst_rect:
height:350 width:720 x:0 y:0
[DML]:DLG: get_surf_rq_param: surf_linear = 1[DML]:DLG:
get_surf_rq_param: surf_vert = 0[DML]:DLG: get_surf_rq_param:
blk256_width = 64[DML]:DLG: get_surf_rq_param: blk256_height =
1[DML]:DLG: get_surf_rq_param: meta_blk_height = 64[DML]:DLG:
get_surf_rq_param: meta_blk_width = 4096[DML]:DLG:
get_surf_rq_param: meta_surface_bytes = 0[DML]:DLG: get_surf_rq_param:
meta_pte_req_per_frame_ub = 1[DML]:DLG: get_surf_rq_param:
meta_pte_bytes_per_frame_ub = 64[DML]:DLG: handle_det_buf_split: req128_l =
0[DML]:DLG: handle_det_buf_split: req128_c = 0[DML]:DLG: handle_det_buf_split:
full_swath_bytes_packed_l = 1792[DML]:DLG: handle_det_buf_split:
full_swath_bytes_packed_c = 0[DML]:DML_RQ_DLG_CALC: ***************************
[DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_PARAM_ST
[DML]:DML_RQ_DLG_CALC: <LUMA>
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 8192
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 1024
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 2048
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 256
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: <CHROMA> ===
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 0
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: <LUMA>
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: swath_width_ub = 448
[DML]:DML_RQ_DLG_CALC: swath_height = 1
[DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 7
[DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 64
[DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 1
[DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 1
[DML]:DML_RQ_DLG_CALC: dpte_row_height = 128
[DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 64
[DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 1
[DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 2
[DML]:DML_RQ_DLG_CALC: meta_row_height = 8
[DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 128
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: <CHROMA>
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: swath_width_ub = 0
[DML]:DML_RQ_DLG_CALC: swath_height = 1
[DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_row_height = 0
[DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_row_height = 0
[DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: <LUMA>
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST
[DML]:DML_RQ_DLG_CALC: full_swath_bytes = 1792
[DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 3584
[DML]:DML_RQ_DLG_CALC: blk256_width = 64
[DML]:DML_RQ_DLG_CALC: blk256_height = 1
[DML]:DML_RQ_DLG_CALC: req_width = 0
[DML]:DML_RQ_DLG_CALC: req_height = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: <CHROMA>
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST
[DML]:DML_RQ_DLG_CALC: full_swath_bytes = 0
[DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 0
[DML]:DML_RQ_DLG_CALC: blk256_width = 0
[DML]:DML_RQ_DLG_CALC: blk256_height = 0
[DML]:DML_RQ_DLG_CALC: req_width = 0
[DML]:DML_RQ_DLG_CALC: req_height = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: ***************************
[DML]:DLG: extract_rq_sizing_regs: rq_sizing param[DML]:DML_RQ_DLG_CALC:
=====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 8192
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 1024
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 2048
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 256
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DLG: dml1_rq_dlg_get_dlg_params: cstate_en = 1[DML]:DLG:
dml1_rq_dlg_get_dlg_params: pstate_en = 1[DML]:DLG: dml1_rq_dlg_get_dlg_params:
vm_en = 1[DML]:DLG: dml1_rq_dlg_get_dlg_params: iflip_en = 0[DML]:DLG:
dml1_rq_dlg_get_dlg_params: dppclk_freq_in_mhz = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: dispclk_freq_in_mhz = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: refclk_freq_in_mhz = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: pclk_freq_in_mhz = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: interlaced = 0[DML]:DLG:
dml1_rq_dlg_get_dlg_params: min_dcfclk_mhz =
f[DML]:DLG: dml1_rq_dlg_get_dlg_params: min_ttu_vblank
= f[DML]:DLG: dml1_rq_dlg_get_dlg_params: min_dst_y_ttu_vblank
= f[DML]:DLG: dml1_rq_dlg_get_dlg_params: t_calc_us
= f[DML]:DLG: dml1_rq_dlg_get_dlg_params:
disp_dlg_regs->min_dst_y_next_start = 0x66f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: ref_freq_to_pix_freq =
f[DML]:DLG: dml1_rq_dlg_get_dlg_params: htotal
= 900[DML]:DLG: dml1_rq_dlg_get_dlg_params: pixel_rate_delay_subtotal
= 218[DML]:DLG: dml1_rq_dlg_get_dlg_params: dst_x_after_scaler
= 578[DML]:DLG: dml1_rq_dlg_get_dlg_params: dst_y_after_scaler
= 0[DML]:DLG: dml1_rq_dlg_get_dlg_params:
soc.sr_enter_plus_exit_time_us = f[DML]:DLG: dml1_rq_dlg_get_dlg_params:
soc.dram_clock_change_latency_us = f[DML]:DLG: dml1_rq_dlg_get_dlg_params:
soc.urgent_latency_us = f[DML]:DLG: dml1_rq_dlg_get_dlg_params:
swath_height_l = 1[DML]:DLG: dml1_rq_dlg_get_dlg_params: t_srx_delay_us
= f[DML]:DLG: dml1_rq_dlg_get_dlg_params: line_time_in_us = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: vupdate_offset = 225[DML]:DLG:
dml1_rq_dlg_get_dlg_params: vupdate_width = 89[DML]:DLG:
dml1_rq_dlg_get_dlg_params: vready_offset = 0[DML]:DLG:
dml1_rq_dlg_get_dlg_params: line_time_in_us = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: line_wait = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: line_o = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: line_setup = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: line_calc = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: dst_y_prefetch (before rnd) = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: dst_y_prefetch (after rnd) = f[DML]:DLG:
get_swath_need: swath_height = 1[DML]:DLG: get_swath_need: vinit
= f[DML]:DLG: get_swath_need: max_num_sw = 1[DML]:DLG:
get_swath_need: max_partial_sw = 1[DML]:DLG: dml1_rq_dlg_get_dlg_params:
sw_bytes_ub_l = 3584[DML]:DLG: dml1_rq_dlg_get_dlg_params:
sw_bytes_ub_c = 0[DML]:DLG: dml1_rq_dlg_get_dlg_params: sw_bytes
= 3584[DML]:DLG: dml1_rq_dlg_get_dlg_params: vm_bytes
= 64[DML]:DLG: dml1_rq_dlg_get_dlg_params: meta_row_bytes =
128[DML]:DLG: dml1_rq_dlg_get_dlg_params: dpte_row_bytes =
64[DML]:DLG: dml1_rq_dlg_get_dlg_params: disp_dlg_regs->dst_y_after_scaler
= 0x0[DML]:DLG: dml1_rq_dlg_get_dlg_params:
disp_dlg_regs->refcyc_x_after_scaler = 0x3d3[DML]:DLG:
dml1_rq_dlg_get_dlg_params: disp_dlg_regs->dst_y_prefetch = 45[DML]:DLG:
dml1_rq_dlg_get_dlg_params: lsw_l = 2[DML]:DLG:
dml1_rq_dlg_get_dlg_params: lsw_c = 0[DML]:DLG:
dml1_rq_dlg_get_dlg_params: dpte_bytes_per_row_ub_l = 64[DML]:DLG:
dml1_rq_dlg_get_dlg_params: dpte_bytes_per_row_ub_c = 0[DML]:DLG:
dml1_rq_dlg_get_dlg_params: prefetch_bw = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: flip_bw = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: t_pre_us = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: t_vm_us = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: t_r0_us = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: dst_y_per_vm_vblank = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: dst_y_per_row_vblank = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: dst_y_prefetch = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: lsw = f[DML]:DLG: get_vratio_pre: max_num_sw
= 1[DML]:DLG: get_vratio_pre: max_partial_sw = 1[DML]:DLG: get_vratio_pre:
swath_height = 1[DML]:DLG: get_vratio_pre: vinit =
f[DML]:DLG: get_vratio_pre: vratio_pre = f[DML]:WARNING_DLG:
get_vratio_pre: vratio_pre= f < 1.0, set to 1.0[DML]:DLG:
dml1_rq_dlg_get_dlg_params: vratio_pre_l= f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: vratio_pre_c= f[DML]:DLG: get_refcyc_per_delivery:
refclk_freq_in_mhz = f[DML]:DLG: get_refcyc_per_delivery: pclk_freq_in_mhz
= f[DML]:DLG: get_refcyc_per_delivery: recout_width = 360[DML]:DLG:
get_refcyc_per_delivery: vratio = f[DML]:DLG:
get_refcyc_per_delivery: req_per_swath_ub = 1[DML]:DLG:
get_refcyc_per_delivery: refcyc_per_delivery= f[DML]:DLG:
get_refcyc_per_delivery: refclk_freq_in_mhz = f[DML]:DLG:
get_refcyc_per_delivery: pclk_freq_in_mhz = f[DML]:DLG:
get_refcyc_per_delivery: recout_width = 360[DML]:DLG:
get_refcyc_per_delivery: vratio = f[DML]:DLG:
get_refcyc_per_delivery: req_per_swath_ub = 1[DML]:DLG:
get_refcyc_per_delivery: refcyc_per_delivery= f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: full_recout_width = 360[DML]:DLG:
dml1_rq_dlg_get_dlg_params: hscale_pixel_rate_l = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: refcyc_per_line_delivery_pre_l = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: refcyc_per_line_delivery_l = f[DML]:DLG:
get_refcyc_per_delivery: refclk_freq_in_mhz = f[DML]:DLG:
get_refcyc_per_delivery: pclk_freq_in_mhz = f[DML]:DLG:
get_refcyc_per_delivery: recout_width = 360[DML]:DLG:
get_refcyc_per_delivery: vratio = f[DML]:DLG:
get_refcyc_per_delivery: req_per_swath_ub = 7[DML]:DLG:
get_refcyc_per_delivery: refcyc_per_delivery= f[DML]:DLG:
get_refcyc_per_delivery: refclk_freq_in_mhz = f[DML]:DLG:
get_refcyc_per_delivery: pclk_freq_in_mhz = f[DML]:DLG:
get_refcyc_per_delivery: recout_width = 360[DML]:DLG:
get_refcyc_per_delivery: vratio = f[DML]:DLG:
get_refcyc_per_delivery: req_per_swath_ub = 7[DML]:DLG:
get_refcyc_per_delivery: refcyc_per_delivery= f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: refcyc_per_req_delivery_pre_l = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: refcyc_per_req_delivery_l = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: cur0_req_width = 64[DML]:DLG:
dml1_rq_dlg_get_dlg_params: cur0_width_ub = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: cur0_req_per_width = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: hactive_cur0 = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: refcyc_per_req_delivery_pre_cur0 = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: refcyc_per_req_delivery_cur0 =
f[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_TTU_REGS_ST
[DML]:DML_RQ_DLG_CALC: qos_level_low_wm = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_high_wm = 0x17d5
[DML]:DML_RQ_DLG_CALC: min_ttu_vblank = 0x50e
[DML]:DML_RQ_DLG_CALC: qos_level_flip = 0xe
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_l = 0x15cab
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_l = 0x15cab
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_cur0 = 0x1b1e5
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur0 = 0x1b1e5
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_cur1 = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur1 = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_l = 0x8
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_l = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_c = 0x8
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_c = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_cur0 = 0x8
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_cur0 = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_cur1 = 0x0
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_cur1 = 0x0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DLG_REGS_ST
[DML]:DML_RQ_DLG_CALC: refcyc_h_blank_end = 0x112
[DML]:DML_RQ_DLG_CALC: dlg_vblank_end = 0x3d
[DML]:DML_RQ_DLG_CALC: min_dst_y_next_start = 0x66f
[DML]:DML_RQ_DLG_CALC: refcyc_per_htotal = 0x5f56c
[DML]:DML_RQ_DLG_CALC: refcyc_x_after_scaler = 0x3d3
[DML]:DML_RQ_DLG_CALC: dst_y_after_scaler = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_prefetch = 0x2d
[DML]:DML_RQ_DLG_CALC: dst_y_per_vm_vblank = 0x1
[DML]:DML_RQ_DLG_CALC: dst_y_per_row_vblank = 0x3
[DML]:DML_RQ_DLG_CALC: dst_y_per_vm_flip = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_per_row_flip = 0x0
[DML]:DML_RQ_DLG_CALC: ref_freq_to_pix_freq = 0xd8f2f
[DML]:DML_RQ_DLG_CALC: vratio_prefetch = 0x80000
[DML]:DML_RQ_DLG_CALC: vratio_prefetch_c = 0x80000
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_vblank_l = 0x478
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_vblank_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_l = 0x478
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_c = 0x478
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_flip_l = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_flip_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_flip_l = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_flip_c = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_per_pte_row_nom_l = 0x200
[DML]:DML_RQ_DLG_CALC: dst_y_per_pte_row_nom_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_nom_l = 0x2fab6
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_nom_c = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_per_meta_row_nom_l = 0x20
[DML]:DML_RQ_DLG_CALC: dst_y_per_meta_row_nom_c = 0x20
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_nom_l = 0x2fab
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_nom_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_pre_l = 0x262
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_pre_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_l = 0x262
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_c = 0x0
[DML]:DML_RQ_DLG_CALC: chunk_hdl_adjust_cur0 = 0x3
[DML]:DML_RQ_DLG_CALC: dst_y_offset_cur1 = 0x0
[DML]:DML_RQ_DLG_CALC: chunk_hdl_adjust_cur1 = 0x0
[DML]:DML_RQ_DLG_CALC: vready_after_vcount0 = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_delta_drq_limit = 0x0
[DML]:DML_RQ_DLG_CALC: xfc_reg_transfer_delay = 0x0
[DML]:DML_RQ_DLG_CALC: xfc_reg_precharge_delay = 0x0
[DML]:DML_RQ_DLG_CALC: xfc_reg_remote_surface_flip_latency = 0x0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DLG: get_surf_rq_param: surf_linear = 1[DML]:DLG:
get_surf_rq_param: surf_vert = 0[DML]:DLG: get_surf_rq_param:
blk256_width = 64[DML]:DLG: get_surf_rq_param: blk256_height =
1[DML]:DLG: get_surf_rq_param: meta_blk_height = 64[DML]:DLG:
get_surf_rq_param: meta_blk_width = 4096[DML]:DLG:
get_surf_rq_param: meta_surface_bytes = 0[DML]:DLG: get_surf_rq_param:
meta_pte_req_per_frame_ub = 1[DML]:DLG: get_surf_rq_param:
meta_pte_bytes_per_frame_ub = 64[DML]:DLG: handle_det_buf_split: req128_l =
0[DML]:DLG: handle_det_buf_split: req128_c = 0[DML]:DLG: handle_det_buf_split:
full_swath_bytes_packed_l = 1792[DML]:DLG: handle_det_buf_split:
full_swath_bytes_packed_c = 0[DML]:DML_RQ_DLG_CALC: ***************************
[DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_PARAM_ST
[DML]:DML_RQ_DLG_CALC: <LUMA>
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 8192
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 1024
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 2048
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 256
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: <CHROMA> ===
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 0
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: <LUMA>
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: swath_width_ub = 448
[DML]:DML_RQ_DLG_CALC: swath_height = 1
[DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 7
[DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 64
[DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 1
[DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 1
[DML]:DML_RQ_DLG_CALC: dpte_row_height = 128
[DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 64
[DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 1
[DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 2
[DML]:DML_RQ_DLG_CALC: meta_row_height = 8
[DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 128
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: <CHROMA>
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: swath_width_ub = 0
[DML]:DML_RQ_DLG_CALC: swath_height = 1
[DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_row_height = 0
[DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_row_height = 0
[DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: <LUMA>
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST
[DML]:DML_RQ_DLG_CALC: full_swath_bytes = 1792
[DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 3584
[DML]:DML_RQ_DLG_CALC: blk256_width = 64
[DML]:DML_RQ_DLG_CALC: blk256_height = 1
[DML]:DML_RQ_DLG_CALC: req_width = 0
[DML]:DML_RQ_DLG_CALC: req_height = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: <CHROMA>
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST
[DML]:DML_RQ_DLG_CALC: full_swath_bytes = 0
[DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 0
[DML]:DML_RQ_DLG_CALC: blk256_width = 0
[DML]:DML_RQ_DLG_CALC: blk256_height = 0
[DML]:DML_RQ_DLG_CALC: req_width = 0
[DML]:DML_RQ_DLG_CALC: req_height = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: ***************************
[DML]:DLG: extract_rq_sizing_regs: rq_sizing param[DML]:DML_RQ_DLG_CALC:
=====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 8192
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 1024
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 2048
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 256
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DLG: dml1_rq_dlg_get_dlg_params: cstate_en = 1[DML]:DLG:
dml1_rq_dlg_get_dlg_params: pstate_en = 1[DML]:DLG: dml1_rq_dlg_get_dlg_params:
vm_en = 1[DML]:DLG: dml1_rq_dlg_get_dlg_params: iflip_en = 0[DML]:DLG:
dml1_rq_dlg_get_dlg_params: dppclk_freq_in_mhz = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: dispclk_freq_in_mhz = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: refclk_freq_in_mhz = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: pclk_freq_in_mhz = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: interlaced = 0[DML]:DLG:
dml1_rq_dlg_get_dlg_params: min_dcfclk_mhz =
f[DML]:DLG: dml1_rq_dlg_get_dlg_params: min_ttu_vblank
= f[DML]:DLG: dml1_rq_dlg_get_dlg_params: min_dst_y_ttu_vblank
= f[DML]:DLG: dml1_rq_dlg_get_dlg_params: t_calc_us
= f[DML]:DLG: dml1_rq_dlg_get_dlg_params:
disp_dlg_regs->min_dst_y_next_start = 0x66f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: ref_freq_to_pix_freq =
f[DML]:DLG: dml1_rq_dlg_get_dlg_params: htotal
= 900[DML]:DLG: dml1_rq_dlg_get_dlg_params: pixel_rate_delay_subtotal
= 218[DML]:DLG: dml1_rq_dlg_get_dlg_params: dst_x_after_scaler
= 578[DML]:DLG: dml1_rq_dlg_get_dlg_params: dst_y_after_scaler
= 0[DML]:DLG: dml1_rq_dlg_get_dlg_params:
soc.sr_enter_plus_exit_time_us = f[DML]:DLG: dml1_rq_dlg_get_dlg_params:
soc.dram_clock_change_latency_us = f[DML]:DLG: dml1_rq_dlg_get_dlg_params:
soc.urgent_latency_us = f[DML]:DLG: dml1_rq_dlg_get_dlg_params:
swath_height_l = 1[DML]:DLG: dml1_rq_dlg_get_dlg_params: t_srx_delay_us
= f[DML]:DLG: dml1_rq_dlg_get_dlg_params: line_time_in_us = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: vupdate_offset = 225[DML]:DLG:
dml1_rq_dlg_get_dlg_params: vupdate_width = 89[DML]:DLG:
dml1_rq_dlg_get_dlg_params: vready_offset = 0[DML]:DLG:
dml1_rq_dlg_get_dlg_params: line_time_in_us = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: line_wait = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: line_o = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: line_setup = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: line_calc = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: dst_y_prefetch (before rnd) = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: dst_y_prefetch (after rnd) = f[DML]:DLG:
get_swath_need: swath_height = 1[DML]:DLG: get_swath_need: vinit
= f[DML]:DLG: get_swath_need: max_num_sw = 1[DML]:DLG:
get_swath_need: max_partial_sw = 1[DML]:DLG: dml1_rq_dlg_get_dlg_params:
sw_bytes_ub_l = 3584[DML]:DLG: dml1_rq_dlg_get_dlg_params:
sw_bytes_ub_c = 0[DML]:DLG: dml1_rq_dlg_get_dlg_params: sw_bytes
= 3584[DML]:DLG: dml1_rq_dlg_get_dlg_params: vm_bytes
= 64[DML]:DLG: dml1_rq_dlg_get_dlg_params: meta_row_bytes =
128[DML]:DLG: dml1_rq_dlg_get_dlg_params: dpte_row_bytes =
64[DML]:DLG: dml1_rq_dlg_get_dlg_params: disp_dlg_regs->dst_y_after_scaler
= 0x0[DML]:DLG: dml1_rq_dlg_get_dlg_params:
disp_dlg_regs->refcyc_x_after_scaler = 0x3d3[DML]:DLG:
dml1_rq_dlg_get_dlg_params: disp_dlg_regs->dst_y_prefetch = 45[DML]:DLG:
dml1_rq_dlg_get_dlg_params: lsw_l = 2[DML]:DLG:
dml1_rq_dlg_get_dlg_params: lsw_c = 0[DML]:DLG:
dml1_rq_dlg_get_dlg_params: dpte_bytes_per_row_ub_l = 64[DML]:DLG:
dml1_rq_dlg_get_dlg_params: dpte_bytes_per_row_ub_c = 0[DML]:DLG:
dml1_rq_dlg_get_dlg_params: prefetch_bw = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: flip_bw = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: t_pre_us = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: t_vm_us = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: t_r0_us = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: dst_y_per_vm_vblank = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: dst_y_per_row_vblank = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: dst_y_prefetch = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: lsw = f[DML]:DLG: get_vratio_pre: max_num_sw
= 1[DML]:DLG: get_vratio_pre: max_partial_sw = 1[DML]:DLG: get_vratio_pre:
swath_height = 1[DML]:DLG: get_vratio_pre: vinit =
f[DML]:DLG: get_vratio_pre: vratio_pre = f[DML]:WARNING_DLG:
get_vratio_pre: vratio_pre= f < 1.0, set to 1.0[DML]:DLG:
dml1_rq_dlg_get_dlg_params: vratio_pre_l= f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: vratio_pre_c= f[DML]:DLG: get_refcyc_per_delivery:
refclk_freq_in_mhz = f[DML]:DLG: get_refcyc_per_delivery: pclk_freq_in_mhz
= f[DML]:DLG: get_refcyc_per_delivery: recout_width = 360[DML]:DLG:
get_refcyc_per_delivery: vratio = f[DML]:DLG:
get_refcyc_per_delivery: req_per_swath_ub = 1[DML]:DLG:
get_refcyc_per_delivery: refcyc_per_delivery= f[DML]:DLG:
get_refcyc_per_delivery: refclk_freq_in_mhz = f[DML]:DLG:
get_refcyc_per_delivery: pclk_freq_in_mhz = f[DML]:DLG:
get_refcyc_per_delivery: recout_width = 360[DML]:DLG:
get_refcyc_per_delivery: vratio = f[DML]:DLG:
get_refcyc_per_delivery: req_per_swath_ub = 1[DML]:DLG:
get_refcyc_per_delivery: refcyc_per_delivery= f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: full_recout_width = 360[DML]:DLG:
dml1_rq_dlg_get_dlg_params: hscale_pixel_rate_l = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: refcyc_per_line_delivery_pre_l = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: refcyc_per_line_delivery_l = f[DML]:DLG:
get_refcyc_per_delivery: refclk_freq_in_mhz = f[DML]:DLG:
get_refcyc_per_delivery: pclk_freq_in_mhz = f[DML]:DLG:
get_refcyc_per_delivery: recout_width = 360[DML]:DLG:
get_refcyc_per_delivery: vratio = f[DML]:DLG:
get_refcyc_per_delivery: req_per_swath_ub = 7[DML]:DLG:
get_refcyc_per_delivery: refcyc_per_delivery= f[DML]:DLG:
get_refcyc_per_delivery: refclk_freq_in_mhz = f[DML]:DLG:
get_refcyc_per_delivery: pclk_freq_in_mhz = f[DML]:DLG:
get_refcyc_per_delivery: recout_width = 360[DML]:DLG:
get_refcyc_per_delivery: vratio = f[DML]:DLG:
get_refcyc_per_delivery: req_per_swath_ub = 7[DML]:DLG:
get_refcyc_per_delivery: refcyc_per_delivery= f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: refcyc_per_req_delivery_pre_l = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: refcyc_per_req_delivery_l = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: cur0_req_width = 64[DML]:DLG:
dml1_rq_dlg_get_dlg_params: cur0_width_ub = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: cur0_req_per_width = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: hactive_cur0 = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: refcyc_per_req_delivery_pre_cur0 = f[DML]:DLG:
dml1_rq_dlg_get_dlg_params: refcyc_per_req_delivery_cur0 =
f[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_TTU_REGS_ST
[DML]:DML_RQ_DLG_CALC: qos_level_low_wm = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_high_wm = 0x17d5
[DML]:DML_RQ_DLG_CALC: min_ttu_vblank = 0x50e
[DML]:DML_RQ_DLG_CALC: qos_level_flip = 0xe
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_l = 0x15cab
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_l = 0x15cab
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_cur0 = 0x1b1e5
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur0 = 0x1b1e5
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_cur1 = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur1 = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_l = 0x8
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_l = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_c = 0x8
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_c = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_cur0 = 0x8
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_cur0 = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_cur1 = 0x0
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_cur1 = 0x0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DLG_REGS_ST
[DML]:DML_RQ_DLG_CALC: refcyc_h_blank_end = 0x112
[DML]:DML_RQ_DLG_CALC: dlg_vblank_end = 0x3d
[DML]:DML_RQ_DLG_CALC: min_dst_y_next_start = 0x66f
[DML]:DML_RQ_DLG_CALC: refcyc_per_htotal = 0x5f56c
[DML]:DML_RQ_DLG_CALC: refcyc_x_after_scaler = 0x3d3
[DML]:DML_RQ_DLG_CALC: dst_y_after_scaler = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_prefetch = 0x2d
[DML]:DML_RQ_DLG_CALC: dst_y_per_vm_vblank = 0x1
[DML]:DML_RQ_DLG_CALC: dst_y_per_row_vblank = 0x3
[DML]:DML_RQ_DLG_CALC: dst_y_per_vm_flip = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_per_row_flip = 0x0
[DML]:DML_RQ_DLG_CALC: ref_freq_to_pix_freq = 0xd8f2f
[DML]:DML_RQ_DLG_CALC: vratio_prefetch = 0x80000
[DML]:DML_RQ_DLG_CALC: vratio_prefetch_c = 0x80000
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_vblank_l = 0x478
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_vblank_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_l = 0x478
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_c = 0x478
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_flip_l = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_flip_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_flip_l = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_flip_c = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_per_pte_row_nom_l = 0x200
[DML]:DML_RQ_DLG_CALC: dst_y_per_pte_row_nom_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_nom_l = 0x2fab6
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_nom_c = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_per_meta_row_nom_l = 0x20
[DML]:DML_RQ_DLG_CALC: dst_y_per_meta_row_nom_c = 0x20
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_nom_l = 0x2fab
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_nom_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_pre_l = 0x262
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_pre_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_l = 0x262
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_c = 0x0
[DML]:DML_RQ_DLG_CALC: chunk_hdl_adjust_cur0 = 0x3
[DML]:DML_RQ_DLG_CALC: dst_y_offset_cur1 = 0x0
[DML]:DML_RQ_DLG_CALC: chunk_hdl_adjust_cur1 = 0x0
[DML]:DML_RQ_DLG_CALC: vready_after_vcount0 = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_delta_drq_limit = 0x0
[DML]:DML_RQ_DLG_CALC: xfc_reg_transfer_delay = 0x0
[DML]:DML_RQ_DLG_CALC: xfc_reg_precharge_delay = 0x0
[DML]:DML_RQ_DLG_CALC: xfc_reg_remote_surface_flip_latency = 0x0
[DML]:DML_RQ_DLG_CALC: =====================================
[drm] No FB bound
[drm] No FB bound
[drm] No FB bound
[drm] No FB bound
[drm] No FB bound
[drm] amdgpu_crtc id:0 crtc_state_flags: enable:1, active:1, planes_changed:1,
mode_changed:1,active_changed:1,connectors_changed:1
[drm] Atomic commit: SET crtc id 0: [0xffff80000066c800]
[drm] amdgpu_crtc id:1 crtc_state_flags: enable:0, active:0, planes_changed:0,
mode_changed:0,active_changed:0,connectors_changed:0
[drm] amdgpu_crtc id:2 crtc_state_flags: enable:0, active:0, planes_changed:0,
mode_changed:0,active_changed:0,connectors_changed:0
[drm] dc_commit_state: 1 streams
[drm] core_stream 0x0xffff800000127800: src: 0, 0, 720, 350; dst: 0, 0, 720,
350, colorSpace:1
[drm] pix_clk_khz: 28320, h_total: 900, v_total: 449, pixelencoder:1,
displaycolorDepth:2
[drm] sink name: DELL 828FI, serial: 808863544
[drm] link: 2
[drm] REG_WAIT taking a while: 5ms in optc1_disable_crtc line:513
[BIOS]:set_pixel_clock_v7:program display clock = 0colorDepth = 0
[BIOS]:set_pixel_clock_v7:program display clock = 0colorDepth = 0
[BIOS]:set_pixel_clock_v7:program display clock = 0colorDepth = 0
[BIOS]:set_pixel_clock_v7:program display clock = 0colorDepth = 0
[BANDWIDTH_CALCS]: dcf_clk for voltage = 300000
[BIOS]:set_dce_clock_v2_1:target_clock_frequency = 100000clock_type = 0
[BIOS]:set_dce_clock_v2_1:target_clock_frequency = 0clock_type = 1
[BANDWIDTH_CALCS]:URGENCY_WATERMARK_A calculated =6958
HW register value = 0x14d
[BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_A calculated =14958
HW register value = 0x2cd
[BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_A calculated =21958
HW register value = 0x41d
[BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_A calculated =21208
HW register value = 0x3f9
[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_A calculated =23958
HW register value = 0x47d
[BANDWIDTH_CALCS]:URGENCY_WATERMARK_B calculated =6958
HW register value = 0x14d
[BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_B calculated =14958
HW register value = 0x2cd
[BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_B calculated =21958
HW register value = 0x41d
[BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_B calculated =21208
HW register value = 0x3f9
[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_B calculated =23958
HW register value = 0x47d
[BANDWIDTH_CALCS]:URGENCY_WATERMARK_C calculated =6958
HW register value = 0x14d
[BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_C calculated =14958
HW register value = 0x2cd
[BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_C calculated =21958
HW register value = 0x41d
[BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_C calculated =21208
HW register value = 0x3f9
[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_C calculated =23958
HW register value = 0x47d
[BANDWIDTH_CALCS]:URGENCY_WATERMARK_D calculated =6958
HW register value = 0x14d
[BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_D calculated =14958
HW register value = 0x2cd
[BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_D calculated =21958
HW register value = 0x41d
[BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_D calculated =21208
HW register value = 0x3f9
[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_D calculated =23958
HW register value = 0x47d
[BIOS]:set_pixel_clock_v7:program display clock = 28320colorDepth = 0
[BIOS]:transmitter_control_v1_6:ps.param.symclk_10khz = 16200
[drm] Link: 2 eDP panel mode supported: 0 eDP panel mode enabled: 0
[HW_LINK_TRAINING]:dpcd_set_link_settings
100 rate = 6
101 lane = 1
107 spread = 10
[HW_LINK_TRAINING]:dpcd_set_lt_pattern_and_lane_settings
102 pattern = 1
[HW_LINK_TRAINING]:dpcd_set_lt_pattern_and_lane_settings:
103 VS set = 0 PE set = 0 max VS Reached = 0 max PE Reached = 0
[HW_LINK_TRAINING]:wait_for_training_aux_rd_interval:
wait = 100
[HW_LINK_TRAINING]:get_lane_status_and_drive_settings:
202 Lane01Status = 1
203 Lane23Status = 0
[HW_LINK_TRAINING]:get_lane_status_and_drive_settings:
206 Lane01AdjustRequest = 0
207 Lane23AdjustRequest = 0
[HW_LINK_TRAINING]:dpcd_set_lt_pattern_and_lane_settings
102 pattern = 2
[HW_LINK_TRAINING]:dpcd_set_lt_pattern_and_lane_settings:
103 VS set = 0 PE set = 0 max VS Reached = 0 max PE Reached = 0
[HW_LINK_TRAINING]:wait_for_training_aux_rd_interval:
wait = 400
[HW_LINK_TRAINING]:get_lane_status_and_drive_settings:
202 Lane01Status = 7
203 Lane23Status = 0
[HW_LINK_TRAINING]:get_lane_status_and_drive_settings:
206 Lane01AdjustRequest = 0
207 Lane23AdjustRequest = 0
[HW_LINK_TRAINING]:dpcd_set_training_pattern
102 pattern = 0
[drm] RBRx1 pass VS=0, PE=0[drm] Un-gated front end for pipe 0
[drm] Un-gated front end for pipe 2
[drm] {720x350,
900x449@28320Khz}[BIOS]:set_dce_clock_v2_1:target_clock_frequency =
100000clock_type = 0
[BIOS]:set_dce_clock_v2_1:target_clock_frequency = 0clock_type = 1
[BANDWIDTH_CALCS]: dcf_clk for voltage = 300000
[BANDWIDTH_CALCS]:URGENCY_WATERMARK_A calculated =6958
HW register value = 0x14d
[BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_A calculated =14958
HW register value = 0x2cd
[BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_A calculated =21958
HW register value = 0x41d
[BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_A calculated =21208
HW register value = 0x3f9
[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_A calculated =23958
HW register value = 0x47d
[BANDWIDTH_CALCS]:URGENCY_WATERMARK_B calculated =6958
HW register value = 0x14d
[BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_B calculated =14958
HW register value = 0x2cd
[BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_B calculated =21958
HW register value = 0x41d
[BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_B calculated =21208
HW register value = 0x3f9
[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_B calculated =23958
HW register value = 0x47d
[BANDWIDTH_CALCS]:URGENCY_WATERMARK_C calculated =6958
HW register value = 0x14d
[BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_C calculated =14958
HW register value = 0x2cd
[BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_C calculated =21958
HW register value = 0x41d
[BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_C calculated =21208
HW register value = 0x3f9
[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_C calculated =23958
HW register value = 0x47d
[BANDWIDTH_CALCS]:URGENCY_WATERMARK_D calculated =6958
HW register value = 0x14d
[BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_D calculated =14958
HW register value = 0x2cd
[BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_D calculated =21958
HW register value = 0x41d
[BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_D calculated =21208
HW register value = 0x3f9
[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_D calculated =23958
HW register value = 0x47d
[drm] crtc:0, pflip_stat:AMDGPU_FLIP_SUBMITTED
[SCALER]:resource_build_scaling_params: Viewport:
height:350 width:360 x:0 y:0
dst_rect:
height:350 width:720 x:0 y:0
[SCALER]:resource_build_scaling_params: Viewport:
height:350 width:360 x:360 y:0
dst_rect:
height:350 width:720 x:0 y:0
[BIOS]:set_dce_clock_v2_1:target_clock_frequency = 100000clock_type = 0
[BIOS]:set_dce_clock_v2_1:target_clock_frequency = 0clock_type = 1
[BANDWIDTH_CALCS]: dcf_clk for voltage = 300000
[BANDWIDTH_CALCS]:URGENCY_WATERMARK_A calculated =6958
HW register value = 0x14d
[BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_A calculated =14958
HW register value = 0x2cd
[BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_A calculated =21958
HW register value = 0x41d
[BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_A calculated =21208
HW register value = 0x3f9
[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_A calculated =23958
HW register value = 0x47d
[BANDWIDTH_CALCS]:URGENCY_WATERMARK_B calculated =6958
HW register value = 0x14d
[BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_B calculated =14958
HW register value = 0x2cd
[BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_B calculated =21958
HW register value = 0x41d
[BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_B calculated =21208
HW register value = 0x3f9
[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_B calculated =23958
HW register value = 0x47d
[BANDWIDTH_CALCS]:URGENCY_WATERMARK_C calculated =6958
HW register value = 0x14d
[BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_C calculated =14958
HW register value = 0x2cd
[BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_C calculated =21958
HW register value = 0x41d
[BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_C calculated =21208
HW register value = 0x3f9
[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_C calculated =23958
HW register value = 0x47d
[BANDWIDTH_CALCS]:URGENCY_WATERMARK_D calculated =6958
HW register value = 0x14d
[BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_D calculated =14958
HW register value = 0x2cd
[BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_D calculated =21958
HW register value = 0x41d
[BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_D calculated =21208
HW register value = 0x3f9
[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_D calculated =23958
HW register value = 0x47d
[BANDWIDTH_CALCS]:Current: dispclk_khz:100000 max_dppclk_khz:50000
dcfclk_khz:300000
dcfclk_deep_sleep_khz:8000 fclk_khz:400000 socclk_khz:0
[BANDWIDTH_CALCS]:Calculated: dispclk_khz:100000 max_dppclk_khz:50000
dcfclk_khz:300000
dcfclk_deep_sleep_khz:8000 fclk_khz:400000 socclk_khz:0
[drm] Un-gated front end for pipe 0
[drm] Un-gated front end for pipe 2
[BIOS]:set_dce_clock_v2_1:target_clock_frequency = 100000clock_type = 0
[drm] dm_pflip_high_irq - crtc :0[0xffff80000066c800],
pflip_stat:AMDGPU_FLIP_NONE
[BIOS]:set_dce_clock_v2_1:target_clock_frequency = 0clock_type = 1
[BANDWIDTH_CALCS]: dcf_clk for voltage = 300000
[BANDWIDTH_CALCS]:URGENCY_WATERMARK_A calculated =6958
HW register value = 0x14d
[BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_A calculated =14958
HW register value = 0x2cd
[BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_A calculated =21958
HW register value = 0x41d
[BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_A calculated =21208
HW register value = 0x3f9
[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_A calculated =23958
HW register value = 0x47d
[BANDWIDTH_CALCS]:URGENCY_WATERMARK_B calculated =6958
HW register value = 0x14d
[BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_B calculated =14958
HW register value = 0x2cd
[BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_B calculated =21958
HW register value = 0x41d
[BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_B calculated =21208
HW register value = 0x3f9
[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_B calculated =23958
HW register value = 0x47d
[BANDWIDTH_CALCS]:URGENCY_WATERMARK_C calculated =6958
HW register value = 0x14d
[BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_C calculated =14958
HW register value = 0x2cd
[BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_C calculated =21958
HW register value = 0x41d
[BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_C calculated =21208
HW register value = 0x3f9
[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_C calculated =23958
HW register value = 0x47d
[BANDWIDTH_CALCS]:URGENCY_WATERMARK_D calculated =6958
HW register value = 0x14d
[BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_D calculated =14958
HW register value = 0x2cd
[BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_D calculated =21958
HW register value = 0x41d
[BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_D calculated =21208
HW register value = 0x3f9
[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_D calculated =23958
HW register value = 0x47d
amdgpu0: 720x350, 32bpp
wsdisplay0 at amdgpu0 mux 1: console (std, vt100 emulation), using wskbd0
wsdisplay0: screen 1-5 added (std, vt100 emulation)
Automatic boot in progress: starting file system checks.
/dev/sd0a (6bb7ffab3d187e8c.a): file system is clean; not checking
/dev/sd0h (6bb7ffab3d187e8c.h): file system is clean; not checking
/dev/sd0d (6bb7ffab3d187e8c.d): file system is clean; not checking
/dev/sd0e (6bb7ffab3d187e8c.e): file system is clean; not checking
/dev/sd0f (6bb7ffab3d187e8c.f): file system is clean; not checking
/dev/sd0g (6bb7ffab3d187e8c.g): file system is clean; not checking
/dev/sd0i (6bb7ffab3d187e8c.i): file system is clean; not checking
kbd: keyboard mapping set to fr
pf enabled
ddb.panic: 1 -> 0
ddb.log: 1 -> 1
net.inet.ip.forwarding: 0 -> 0
net.inet6.ip6.forwarding: 0 -> 0
starting network
re0: no link.....
re0: 192.168.92.25 lease accepted from 192.168.92.2 (c8:be:19:e2:2c:ed)
reordering libraries: done.
starting early daemons: syslogd pflogd ntpd.
starting RPC daemons:.
savecore: no core dump
checking quotas: done.
clearing /tmp
kern.securelevel: 0 -> 1
turning on accounting
creating runtime link editor directory cache.
preserving editor files.
starting network daemons: sshd smtpd sndiod.
starting local daemons: cron.
Wed Oct 16 13:31:36 CEST 2019
