> Date: Tue, 14 Dec 2021 22:54:48 +0000 > From: Renato Aguiar <ren...@renatoaguiar.net> > > "Mark Kettenis" <mark.kette...@xs4all.nl> writes: > > > > > Does the diff below help? > > > > > > Index: dev/ic/dwiic.c > > =================================================================== > > RCS file: /cvs/src/sys/dev/ic/dwiic.c,v > > retrieving revision 1.13 > > diff -u -p -r1.13 dwiic.c > > --- dev/ic/dwiic.c 7 Nov 2021 14:07:43 -0000 1.13 > > +++ dev/ic/dwiic.c 14 Dec 2021 10:56:37 -0000 > > @@ -153,6 +153,10 @@ dwiic_init(struct dwiic_softc *sc) > > /* disable the adapter */ > > dwiic_enable(sc, 0); > > > > + /* disable interrupts */ > > + dwiic_write(sc, DW_IC_INTR_MASK, 0); > > + dwiic_read(sc, DW_IC_CLR_INTR); > > + > > /* write standard-mode SCL timing parameters */ > > dwiic_write(sc, DW_IC_SS_SCL_HCNT, sc->ss_hcnt); > > dwiic_write(sc, DW_IC_SS_SCL_LCNT, sc->ss_lcnt); > > No, it doesn't. I had also tried disabling interrupts at some other > places during my initial investigation, but I couldn't make them stop > without completely disabling the device.
Are any bits in DW_IC_INTR_STAT set when this happens upon resume?
